drm/i915/fia: FIA registers offset implementation.

The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.

v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)

v3:
- Remove register offset defines. (Jani)
- Update comment. (Anusha)

v4: rebase. Remove comment.(Lucas)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101185557.29585-1-anusha.srivatsa@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 470b6fd39c4c3f1f76d9dda789e13418c4624ff3..672fcdab4d23303d45b6e1d7372aca64762f6184 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2074,8 +2074,10 @@ enum i915_power_well_id {
 #define BXT_PORT_CL2CM_DW6(phy)                _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN     (1 << 28)
 
+#define FIA1_BASE                      0x163000
+
 /* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1            _MMIO(0x1638C0)
+#define PORT_TX_DFLEXDPMLE1            _MMIO(FIA1_BASE + 0x008C0)
 #define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)    (0xf << (4 * (tc_port)))
 #define   DFLEXDPMLE1_DPMLETC_ML0(tc_port)     (1 << (4 * (tc_port)))
 #define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)   (3 << (4 * (tc_port)))
@@ -11097,17 +11099,17 @@ enum skl_power_gate {
                                                _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
                                                _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
 
-#define PORT_TX_DFLEXDPSP                      _MMIO(0x1638A0)
+#define PORT_TX_DFLEXDPSP                      _MMIO(FIA1_BASE + 0x008A0)
 #define   TC_LIVE_STATE_TBT(tc_port)           (1 << ((tc_port) * 8 + 6))
 #define   TC_LIVE_STATE_TC(tc_port)            (1 << ((tc_port) * 8 + 5))
 #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)    ((tc_port) * 8)
 #define   DP_LANE_ASSIGNMENT_MASK(tc_port)     (0xf << ((tc_port) * 8))
 #define   DP_LANE_ASSIGNMENT(tc_port, x)       ((x) << ((tc_port) * 8))
 
-#define PORT_TX_DFLEXDPPMS                             _MMIO(0x163890)
+#define PORT_TX_DFLEXDPPMS                             _MMIO(FIA1_BASE + 0x00890)
 #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)                (1 << (tc_port))
 
-#define PORT_TX_DFLEXDPCSSS                            _MMIO(0x163894)
+#define PORT_TX_DFLEXDPCSSS                    _MMIO(FIA1_BASE + 0x00894)
 #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)         (1 << (tc_port))
 
 #endif /* _I915_REG_H_ */