drm/i915: Move VIDEO_DIP_CTL definitions to their right place.

The bits weren't defined in descending order.
v2: Move definitions in a separate patch (Manasi)

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-2-dhinakaran.pandiyan@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11b273f159c134b657454e090f3cf8da678392e8..bcee91bcfba6dc6413bdb4eacb27d5503cb8493e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4564,6 +4564,15 @@ enum {
 #define   VIDEO_DIP_FREQ_2VSYNC                (2 << 16)
 #define   VIDEO_DIP_FREQ_MASK          (3 << 16)
 /* HSW and later: */
+#define   DRM_DIP_ENABLE               (1 << 28)
+#define   PSR_VSC_BIT_7_SET            (1 << 27)
+#define   VSC_SELECT_MASK              (0x3 << 25)
+#define   VSC_SELECT_SHIFT             25
+#define   VSC_DIP_HW_HEA_DATA          (0 << 25)
+#define   VSC_DIP_HW_HEA_SW_DATA       (1 << 25)
+#define   VSC_DIP_HW_DATA_SW_HEA       (2 << 25)
+#define   VSC_DIP_SW_HEA_DATA          (3 << 25)
+#define   VDIP_ENABLE_PPS              (1 << 24)
 #define   VIDEO_DIP_ENABLE_VSC_HSW     (1 << 20)
 #define   VIDEO_DIP_ENABLE_GCP_HSW     (1 << 16)
 #define   VIDEO_DIP_ENABLE_AVI_HSW     (1 << 12)
@@ -4571,16 +4580,6 @@ enum {
 #define   VIDEO_DIP_ENABLE_GMP_HSW     (1 << 4)
 #define   VIDEO_DIP_ENABLE_SPD_HSW     (1 << 0)
 
-#define  DRM_DIP_ENABLE                        (1 << 28)
-#define  PSR_VSC_BIT_7_SET             (1 << 27)
-#define  VSC_SELECT_MASK               (0x3 << 25)
-#define  VSC_SELECT_SHIFT              25
-#define  VSC_DIP_HW_HEA_DATA           (0 << 25)
-#define  VSC_DIP_HW_HEA_SW_DATA                (1 << 25)
-#define  VSC_DIP_HW_DATA_SW_HEA                (2 << 25)
-#define  VSC_DIP_SW_HEA_DATA           (3 << 25)
-#define  VDIP_ENABLE_PPS               (1 << 24)
-
 /* Panel power sequencing */
 #define PPS_BASE                       0x61200
 #define VLV_PPS_BASE                   (VLV_DISPLAY_BASE + PPS_BASE)