bnx2x: Clear dirty status when booting after UNDI
authorYuval Mintz <yuvalmin@broadcom.com>
Mon, 14 Jan 2013 05:11:41 +0000 (05:11 +0000)
committerDavid S. Miller <davem@davemloft.net>
Tue, 15 Jan 2013 20:07:58 +0000 (15:07 -0500)
Self-tests following boot from SAN have failed as the
UNDI driver might leave some NIG interrupt indications.

This patch does the clean-up, clearing those indications
and allowing the test to pass.

Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Ariel Elior <ariele@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

index f808ed031ee7c6e274a2ecc945a71e15c3384cdc..6578e410cee04a63c9f0b7a5e015ce738ee0673c 100644 (file)
@@ -9854,6 +9854,8 @@ static int bnx2x_prev_unload_common(struct bnx2x *bp)
                                prev_undi = true;
                                /* clear the UNDI indication */
                                REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
+                               /* clear possible idle check errors */
+                               REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
                        }
                }
                /* wait until BRB is empty */
index a01596561d68009a9e391f0c1082fad4ba0a4f32..765e2dcadbdba3e592fe6c4cc28c6eb13f1c24d0 100644 (file)
 /* [R 32] Interrupt register #0 read */
 #define NIG_REG_NIG_INT_STS_0                                   0x103b0
 #define NIG_REG_NIG_INT_STS_1                                   0x103c0
+/* [RC 32] Interrupt register #0 read clear */
+#define NIG_REG_NIG_INT_STS_CLR_0                               0x103b4
 /* [R 32] Legacy E1 and E1H location for parity error mask register. */
 #define NIG_REG_NIG_PRTY_MASK                                   0x103dc
 /* [RW 32] Parity mask register #0 read/write */