drm/radeon/dpm: add debugfs support for KB/KV
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 18 Jul 2013 20:39:53 +0000 (16:39 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Aug 2013 20:30:32 +0000 (16:30 -0400)
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/cikd.h
drivers/gpu/drm/radeon/kv_dpm.c
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h

index 9716ffcded43ff295574f9cc6cec72176cf1f614..259b81c7cdd8b76794a1db25f78a3136b323328e 100644 (file)
 #       define DISP_GAP_MCHG(x)                           ((x) << 24)
 #       define DISP_GAP_MCHG_MASK                         (3 << 24)
 
+#define SMU_VOLTAGE_STATUS                                0xC0200094
+#       define SMU_VOLTAGE_CURRENT_LEVEL_MASK             (0xff << 1)
+#       define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT            1
+
 #define TARGET_AND_CURRENT_PROFILE_INDEX_1                0xC02000F0
 #       define CURR_PCIE_INDEX_MASK                       (0xf << 24)
 #       define CURR_PCIE_INDEX_SHIFT                      24
index 2e4016356dabed16d7700af8ce81853609127847..d584ee4a09adaa695c381a677d3427230dc3777b 100644 (file)
@@ -26,6 +26,7 @@
 #include "cikd.h"
 #include "r600_dpm.h"
 #include "kv_dpm.h"
+#include <linux/seq_file.h>
 
 #define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
 #define KV_MINIMUM_ENGINE_CLOCK         800
@@ -2481,6 +2482,28 @@ int kv_dpm_init(struct radeon_device *rdev)
        return 0;
 }
 
+void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                   struct seq_file *m)
+{
+       struct kv_power_info *pi = kv_get_pi(rdev);
+       u32 current_index =
+               (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
+               CURR_SCLK_INDEX_SHIFT;
+       u32 sclk, tmp;
+       u16 vddc;
+
+       if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
+               seq_printf(m, "invalid dpm profile %d\n", current_index);
+       } else {
+               sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
+               tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
+                       SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
+               vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
+               seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
+                          current_index, sclk, vddc);
+       }
+}
+
 void kv_dpm_print_power_state(struct radeon_device *rdev,
                              struct radeon_ps *rps)
 {
index 2d7bdda90bbabea4de37b83960c7b2dd6b758dda..b25172bc1ef2995b95d11ec15f651f760a7de4f5 100644 (file)
@@ -2640,6 +2640,7 @@ static struct radeon_asic kv_asic = {
                .get_sclk = &kv_dpm_get_sclk,
                .get_mclk = &kv_dpm_get_mclk,
                .print_power_state = &kv_dpm_print_power_state,
+               .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
index b5f4e431c49358b224003a603468f2580b35064c..80ad5d89e4bba07c65295fd099e71c621589d6cc 100644 (file)
@@ -782,5 +782,7 @@ u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
 void kv_dpm_print_power_state(struct radeon_device *rdev,
                              struct radeon_ps *ps);
+void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
+                                                   struct seq_file *m);
 
 #endif