drm/i915/chv: Remove DPIO force latency causing interpair skew issue

Latest version of the "CHV DPIO programming notes" no longer requires writes
to TX DW 11 to fix a +2UI interpair skew issue. The current code from
April 2014 was actually causing additional skew issues between all
TMDS pairs.

ver2: added same treatment to intel_dp.c based on Ville's testing.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8e0d1015fb36524daf31d563b3434257bf91457f..60e8d5d77fc5270a64392f09543dbfe452e783d9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2742,11 +2742,6 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
 
        /* Program Tx lane latency optimal setting*/
        for (i = 0; i < 4; i++) {
-               /* Set the latency optimal bit */
-               data = (i == 1) ? 0x0 : 0x6;
-               vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
-                               data << DPIO_FRC_LATENCY_SHFIT);
-
                /* Set the upar bit */
                data = (i == 1) ? 0x0 : 0x1;
                vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index cacbafdad3abd300a02d2d35e22dcc9fd2de037f..bfabd5fd933424d46e9af6f5de1151f9d0600ad1 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1515,11 +1515,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 
        /* Program Tx latency optimal setting */
        for (i = 0; i < 4; i++) {
-               /* Set the latency optimal bit */
-               data = (i == 1) ? 0x0 : 0x6;
-               vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
-                               data << DPIO_FRC_LATENCY_SHFIT);
-
                /* Set the upar bit */
                data = (i == 1) ? 0x0 : 0x1;
                vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),