drm/i915/guc: Handle default action received over CT

When running on platform with CTB based GuC communication enabled,
GuC to Host event data will be delivered as CT request message.
However, content of the data[1] of this CT message follows format
of the scratch register used in MMIO based communication, so some
code reuse is still possible.

v2:  filter disabled messages (Daniele)

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com> #1
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180327214124.70680-1-michal.wajdeczko@intel.com

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 411c8e910583f282329caa239d00723dde7bd0c0..a00a59a7d9ec10f7a5119282659772998123b215 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -416,6 +416,14 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc)
        I915_WRITE(SOFT_SCRATCH(15), val & ~msg);
        spin_unlock(&guc->irq_lock);
 
+       intel_guc_to_host_process_recv_msg(guc, msg);
+}
+
+void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg)
+{
+       /* Make sure to handle only enabled messages */
+       msg &= guc->msg_enabled_mask;
+
        if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
                   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
                intel_guc_log_handle_flush_event(&guc->log);

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 6dc109ab61bc01c0b52807aded5d87742e8c10df..f1265e122d307b6af8820aa9ee37c74e2f3b0f19 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -163,6 +163,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
 void intel_guc_to_host_event_handler(struct intel_guc *guc);
 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
 void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc);
+void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg);
 int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 int intel_guc_suspend(struct intel_guc *guc);

diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index aa810aded442c4cac2a2a2705c46847707d0d488..e8370846c2c9cd787ebbb63f94c6a8536a82b713 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -694,8 +694,17 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
 static void ct_process_request(struct intel_guc_ct *ct,
                               u32 action, u32 len, const u32 *payload)
 {
+       struct intel_guc *guc = ct_to_guc(ct);
+
        switch (action) {
+       case INTEL_GUC_ACTION_DEFAULT:
+               if (unlikely(len < 1))
+                       goto fail_unexpected;
+               intel_guc_to_host_process_recv_msg(guc, *payload);
+               break;
+
        default:
+fail_unexpected:
                DRM_ERROR("CT: unexpected request %x %*phn\n",
                          action, 4 * len, payload);
                break;