drm/i915/glk: Fix DMC/DC state idleness calculation
authorImre Deak <imre.deak@intel.com>
Tue, 3 Oct 2017 09:51:59 +0000 (12:51 +0300)
committerImre Deak <imre.deak@intel.com>
Wed, 4 Oct 2017 08:38:33 +0000 (11:38 +0300)
According to BSpec GLK like BXT needs to ignore the idle state of cores
before starting the DMC firmware's DC state handler.

Fixes: dbb28b5c3d3c ("drm/i915/DMC/GLK: Load DMC on GLK")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171003095159.711-2-imre.deak@intel.com
drivers/gpu/drm/i915/intel_csr.c

index cdfb624eb82d9e06898e88dff3b13a6b769d65f9..ea5d5c9645a4999c5a524b511b8eb78c6831320c 100644 (file)
@@ -216,7 +216,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 
        mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 
-       if (IS_BROXTON(dev_priv))
+       if (IS_GEN9_LP(dev_priv))
                mask |= DC_STATE_DEBUG_MASK_CORES;
 
        /* The below bit doesn't need to be cleared ever afterwards */