drm/amd/display: move dsc clock from plane_resource to stream_resource

code restructure.

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 33f1a1d972a9b3ff62249e5b02fa10145bb0b9f3..aa04df64522f197d57a65933540ec1a3bb7206ec 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2204,7 +2204,7 @@ bool dcn20_validate_bandwidth(struct dc *dc,
                context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
                                                pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-               context->res_ctx.pipe_ctx[i].plane_res.bw.dscclk_khz =
+               context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
                                context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
 #endif
                context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 2d551a6848f516066491dfed365a25290719cc02..e94f3c1801447b9288609b8ff6be9ed2e83beb77 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -222,15 +222,14 @@ struct resource_pool {
 
 struct dcn_fe_bandwidth {
        int dppclk_khz;
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-       int dscclk_khz;
-#endif
+
 };
 
 struct stream_resource {
        struct output_pixel_processor *opp;
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
        struct display_stream_compressor *dsc;
+       int dscclk_khz;
 #endif
        struct timing_generator *tg;
        struct stream_encoder *stream_enc;