drm/amd/amdgpu: Tidy up gfx_v9_0_enable_sck_slow_down_on_power_down()

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5a301c865bf12d6f0134333d26b219235b9ec1bd..1f95ca8e476bdb43c7068106765177247f968ef3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1856,16 +1856,11 @@ static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *ad
        uint32_t default_data = 0;
 
        default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
-
-       if (enable == true) {
-               data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
-               if(default_data != data)
-                       WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
-       } else {
-               data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
-               if(default_data != data)
-                       WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
-       }
+       data = REG_SET_FIELD(data, RLC_PG_CNTL,
+                            SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
+                            enable ? 1 : 0);
+       if(default_data != data)
+               WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
 }
 
 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,