ARMv7: Mark the PTWs inner WBWA on SMP and WB on UP

There are additional bits to set for the ARMv7 SMP extensions in the
TTBR registers. The IRGN bits order is counter-intuitive but it allows
software built for the ARMv7 base architecture to run on an
implementation with the MP extensions.

Signed-off-by: Tony Thompson <Anthony.Thompson@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index c3f737516836471894e7419cab4fec6d44e1b633..a18aace3299046ed9441578e49ecf770d7c4367d 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,17 +19,23 @@
 
 #include "proc-macros.S"
 
-#define TTB_C          (1 << 0)
 #define TTB_S          (1 << 1)
 #define TTB_RGN_NC     (0 << 3)
 #define TTB_RGN_OC_WBWA        (1 << 3)
 #define TTB_RGN_OC_WT  (2 << 3)
 #define TTB_RGN_OC_WB  (3 << 3)
+#define TTB_NOS                (1 << 5)
+#define TTB_IRGN_NC    ((0 << 0) | (0 << 6))
+#define TTB_IRGN_WBWA  ((0 << 0) | (1 << 6))
+#define TTB_IRGN_WT    ((1 << 0) | (0 << 6))
+#define TTB_IRGN_WB    ((1 << 0) | (1 << 6))
 
 #ifndef CONFIG_SMP
-#define TTB_FLAGS      TTB_C|TTB_RGN_OC_WB             @ mark PTWs cacheable, outer WB
+/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
+#define TTB_FLAGS      TTB_IRGN_WB|TTB_RGN_OC_WB
 #else
-#define TTB_FLAGS      TTB_C|TTB_S|TTB_RGN_OC_WBWA     @ mark PTWs cacheable and shared, outer WBWA
+/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
+#define TTB_FLAGS      TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
 #endif
 
 ENTRY(cpu_v7_proc_init)