staging: mt7621-pci: Add spaces after commas in pci-mt7621.c

Adds spaces after commas in parameter lists in pci-mt7621.c

Signed-off-by: Peter Vernia <peter.vernia@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index c7932ae00db12ff32e37b42d467db81481b32a51..3c7978e4355d0899f637276a17f0a0142118328d 100644 (file)
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -399,10 +399,10 @@ set_phy_for_ssc(void)
                if (reg >= 6) {
                        printk("***** Xtal 25MHz *****\n");
                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);     // RG_PE1_H_PLL_FBKSEL  //Feedback clock select
-                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0,31, 0x18000000);       // RG_PE1_H_LCDDS_PCW_NCPO      //DDS NCPO PCW (for host mode)
-                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0,16, 0x18d);    // RG_PE1_H_LCDDS_SSC_PRD       //DDS SSC dither period control
-                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA     //DDS SSC dither amplitude control
-                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a);     // RG_PE1_H_LCDDS_SSC_DELTA1    //DDS SSC dither amplitude control for initial
+                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);      // RG_PE1_H_LCDDS_PCW_NCPO      //DDS NCPO PCW (for host mode)
+                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);   // RG_PE1_H_LCDDS_SSC_PRD       //DDS SSC dither period control
+                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);    // RG_PE1_H_LCDDS_SSC_DELTA     //DDS SSC dither amplitude control
+                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);    // RG_PE1_H_LCDDS_SSC_DELTA1    //DDS SSC dither amplitude control for initial
                } else {
                        printk("***** Xtal 20MHz *****\n");
                }
@@ -436,10 +436,10 @@ set_phy_for_ssc(void)
                set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);       // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
                if (reg >= 6) {         // 25MHz Xtal
                        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);       // RG_PE1_H_PLL_FBKSEL  //Feedback clock select
-                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO      //DDS NCPO PCW (for host mode)
-                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0,16, 0x18d);      // RG_PE1_H_LCDDS_SSC_PRD       //DDS SSC dither period control
-                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA     //DDS SSC dither amplitude control
-                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a);       // RG_PE1_H_LCDDS_SSC_DELTA1    //DDS SSC dither amplitude control for initial
+                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);        // RG_PE1_H_LCDDS_PCW_NCPO      //DDS NCPO PCW (for host mode)
+                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);     // RG_PE1_H_LCDDS_SSC_PRD       //DDS SSC dither period control
+                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);      // RG_PE1_H_LCDDS_SSC_DELTA     //DDS SSC dither amplitude control
+                       set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);      // RG_PE1_H_LCDDS_SSC_DELTA1    //DDS SSC dither amplitude control for initial
                }
        }
        set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);       // RG_PE1_LCDDS_CLK_PH_INV      //DDS clock inversion