powerpc/mpc85xx: Add TMU device tree support for T1040/T1042

Also add nodes and properties for thermal management support. Meanwhile
preprocessor support is needed using thermal of framework.

Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Reviewed-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts b/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
index 681746efd31ddc7dbb36f66d1453b9b501917fe2..fb6bc02ebb606072a3a503220f7fdac4617ea41f 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
@@ -43,4 +43,4 @@
        interrupt-parent = <&mpic>;
 };
 
-/include/ "t1040si-post.dtsi"
+#include "t1040si-post.dtsi"

diff --git a/arch/powerpc/boot/dts/fsl/t1040qds.dts b/arch/powerpc/boot/dts/fsl/t1040qds.dts
index 4d298659468c7dfeedf668a6039a62395188e75c..5f76edc7838c105565b86e71c30ea0d463289ccf 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1040qds.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040qds.dts
@@ -43,4 +43,4 @@
        interrupt-parent = <&mpic>;
 };
 
-/include/ "t1040si-post.dtsi"
+#include "t1040si-post.dtsi"

diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
index 8f9e65b47515db0eb3a5ddbdbbb8221f2709a5c4..cf194154bbdce37151403052608a29514dace66c 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
@@ -45,4 +45,4 @@
        };
 };
 
-/include/ "t1040si-post.dtsi"
+#include "t1040si-post.dtsi"

diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index d30b3de1cfc57eec5d9f0817eb6a649c2c371ba1..e0f4da55477405daa5f9eb8f1b065187c0af0574 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -32,6 +32,8 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <dt-bindings/thermal/thermal.h>
+
 &bman_fbpr {
        compatible = "fsl,bman-fbpr";
        alloc-ranges = <0 0 0x10000 0>;
@@ -484,6 +486,98 @@
                reg        = <0xea000 0x4000>;
        };
 
+       tmu: tmu@f0000 {
+               compatible = "fsl,qoriq-tmu";
+               reg = <0xf0000 0x1000>;
+               interrupts = <18 2 0 0>;
+               fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
+               fsl,tmu-calibration = <0x00000000 0x00000025
+                                      0x00000001 0x00000028
+                                      0x00000002 0x0000002d
+                                      0x00000003 0x00000031
+                                      0x00000004 0x00000036
+                                      0x00000005 0x0000003a
+                                      0x00000006 0x00000040
+                                      0x00000007 0x00000044
+                                      0x00000008 0x0000004a
+                                      0x00000009 0x0000004f
+                                      0x0000000a 0x00000054
+
+                                      0x00010000 0x0000000d
+                                      0x00010001 0x00000013
+                                      0x00010002 0x00000019
+                                      0x00010003 0x0000001f
+                                      0x00010004 0x00000025
+                                      0x00010005 0x0000002d
+                                      0x00010006 0x00000033
+                                      0x00010007 0x00000043
+                                      0x00010008 0x0000004b
+                                      0x00010009 0x00000053
+
+                                      0x00020000 0x00000010
+                                      0x00020001 0x00000017
+                                      0x00020002 0x0000001f
+                                      0x00020003 0x00000029
+                                      0x00020004 0x00000031
+                                      0x00020005 0x0000003c
+                                      0x00020006 0x00000042
+                                      0x00020007 0x0000004d
+                                      0x00020008 0x00000056
+
+                                      0x00030000 0x00000012
+                                      0x00030001 0x0000001d>;
+               #thermal-sensor-cells = <0>;
+       };
+
+       thermal-zones {
+               cpu_thermal: cpu-thermal {
+                       polling-delay-passive = <1000>;
+                       polling-delay = <5000>;
+
+                       thermal-sensors = <&tmu>;
+
+                       trips {
+                               cpu_alert: cpu-alert {
+                                       temperature = <85000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+                               cpu_crit: cpu-crit {
+                                       temperature = <95000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&cpu_alert>;
+                                       cooling-device =
+                                               <&cpu0 THERMAL_NO_LIMIT
+                                                       THERMAL_NO_LIMIT>;
+                               };
+                               map1 {
+                                       trip = <&cpu_alert>;
+                                       cooling-device =
+                                               <&cpu1 THERMAL_NO_LIMIT
+                                                       THERMAL_NO_LIMIT>;
+                               };
+                               map2 {
+                                       trip = <&cpu_alert>;
+                                       cooling-device =
+                                               <&cpu2 THERMAL_NO_LIMIT
+                                                       THERMAL_NO_LIMIT>;
+                               };
+                               map3 {
+                                       trip = <&cpu_alert>;
+                                       cooling-device =
+                                               <&cpu3 THERMAL_NO_LIMIT
+                                                       THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+       };
+
        scfg: global-utilities@fc000 {
                compatible = "fsl,t1040-scfg";
                reg = <0xfc000 0x1000>;

diff --git a/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts b/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
index b245b31b8279e226616027bc0dc8933ce2050e17..2a5a90dd272e290da584639c10dafac0742ab30d 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
@@ -50,4 +50,4 @@
        };
 };
 
-/include/ "t1040si-post.dtsi"
+#include "t1042si-post.dtsi"

diff --git a/arch/powerpc/boot/dts/fsl/t1042qds.dts b/arch/powerpc/boot/dts/fsl/t1042qds.dts
index 4ab9bbe7c5c5b73196dea1e2fe7460cbcd38c4dc..90a4a73bb905d50712a9d714e8226790c61ea18e 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1042qds.dts
+++ b/arch/powerpc/boot/dts/fsl/t1042qds.dts
@@ -43,4 +43,4 @@
        interrupt-parent = <&mpic>;
 };
 
-/include/ "t1042si-post.dtsi"
+#include "t1042si-post.dtsi"

diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb.dts b/arch/powerpc/boot/dts/fsl/t1042rdb.dts
index 67af56bc5ee980a5c7bf6f6d941688e435d1f38c..8d908e795e4db42c71d5b12d067ae3cbb7b062e7 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1042rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1042rdb.dts
@@ -45,4 +45,4 @@
        };
 };
 
-/include/ "t1042si-post.dtsi"
+#include "t1042si-post.dtsi"

diff --git a/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts b/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
index 2f67677530a44c7e13d2b8939aba7293b9101fc8..98c001019d6a39c8e06cceaabea68687341c579d 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
+++ b/arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
@@ -54,4 +54,4 @@
        };
 };
 
-/include/ "t1042si-post.dtsi"
+#include "t1042si-post.dtsi"

diff --git a/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
index 319b74f29724fa733bc2d800b2c2a0e8fa48508c..a5544f93689c79f74e67bc6677b26f8e7ee862eb 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
@@ -32,6 +32,6 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/include/ "t1040si-post.dtsi"
+#include "t1040si-post.dtsi"
 
 /* Place holder for ethernet related device tree nodes */

diff --git a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
index fcfa38ae5e026e9e44ff876bf3c425f16f7c7a85..6db0ee8b1384f0744ba26e8b6f7a6df771f70eec 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
@@ -76,6 +76,7 @@
                        reg = <0>;
                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
+                       #cooling-cells = <2>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -85,6 +86,7 @@
                        reg = <1>;
                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
+                       #cooling-cells = <2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -94,6 +96,7 @@
                        reg = <2>;
                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
+                       #cooling-cells = <2>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
                        };
@@ -103,6 +106,7 @@
                        reg = <3>;
                        clocks = <&mux3>;
                        next-level-cache = <&L2_4>;
+                       #cooling-cells = <2>;
                        L2_4: l2-cache {
                                next-level-cache = <&cpc>;
                        };