drm/i915: W/A for underruns with WM1+ disabled on icl

Disabling WM1+ on ICL causes tons of underruns with
linear/X-tiled framebuffers. We can avoid this by flipping
on a chicken bit affecting the way the hw fill the FIFO.
This may not be the final solution but should hopefully
avoid some underruns in the meantime.

v2: Apparently PIPE_CHICKEN is icl+ only

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190204202232.27153-1-ville.syrjala@linux.intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ede54fdc1676f89b29c2f9ff03bc88d8f350d2df..12964b0fbc5451b07c750d2e8902ceaf1053fd34 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7618,6 +7618,7 @@ enum {
 #define _PIPEB_CHICKEN                 0x71038
 #define _PIPEC_CHICKEN                 0x72038
 #define  PER_PIXEL_ALPHA_BYPASS_EN     (1 << 7)
+#define  PM_FILL_MAINTAIN_DBUF_FULLNESS        (1 << 0)
 #define PIPE_CHICKEN(pipe)             _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
                                                   _PIPEB_CHICKEN)
 

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dc7a2aa6287466ce7dff0ea4901323e94cd88119..9db931a450f69450d5111668c1a04563b020fc3e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3911,6 +3911,12 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
         */
        tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 
+       /*
+        * W/A for underruns with linear/X-tiled with
+        * WM1+ disabled.
+        */
+       tmp |= PM_FILL_MAINTAIN_DBUF_FULLNESS;
+
        I915_WRITE(PIPE_CHICKEN(pipe), tmp);
 }