#define LPFC_SLI_INTF_IF_TYPE_VIRT 1
};
+struct lpfc_sli_asic_rev {
+ u32 word0;
+#define LPFC_SLI_ASIC_VER_A 0x0
+#define LPFC_SLI_ASIC_VER_B 0x1
+#define LPFC_SLI_ASIC_VER_C 0x2
+#define LPFC_SLI_ASIC_VER_D 0x3
+#define lpfc_sli_asic_ver_SHIFT 4
+#define lpfc_sli_asic_ver_MASK 0x0000000F
+#define lpfc_sli_asic_ver_WORD word0
+};
+
#define LPFC_SLI4_MBX_EMBED true
#define LPFC_SLI4_MBX_NEMBED false
/* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
#define LPFC_SLI_INTF 0x0058
+#define LPFC_SLI_ASIC_VER 0x009C
#define LPFC_CTL_PORT_SEM_OFFSET 0x400
#define lpfc_port_smphr_perr_SHIFT 31
return error;
}
+ if (pci_read_config_dword(pdev, LPFC_SLI_ASIC_VER,
+ &phba->sli4_hba.sli_asic_ver.word0)) {
+ return error;
+ }
+
/* There is no SLI3 failback for SLI4 devices. */
if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
LPFC_SLI_INTF_VALID) {
struct lpfc_pc_sli4_params *sli4_params;
uint32_t mbox_tmo;
int length;
+ bool exp_wqcq_pages = true;
struct lpfc_sli4_parameters *mbx_sli4_parameters;
/*
phba->nvme_support, phba->nvme_embed_pbde,
phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
+ if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
+ LPFC_SLI_INTF_IF_TYPE_2) &&
+ (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
+ LPFC_SLI_INTF_FAMILY_LNCR_A0) &&
+ (bf_get(lpfc_sli_asic_ver, &phba->sli4_hba.sli_asic_ver) ==
+ LPFC_SLI_ASIC_VER_A))
+ exp_wqcq_pages = false;
+
if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
(bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
+ exp_wqcq_pages &&
(sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
phba->enab_exp_wqcq_pages = 1;
else
uint32_t ue_to_sr;
uint32_t ue_to_rp;
struct lpfc_register sli_intf;
+ struct lpfc_register sli_asic_ver;
struct lpfc_pc_sli4_params pc_sli4_params;
struct lpfc_bbscn_params bbscn_params;
struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */