drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask
authorChris Wilson <chris@chris-wilson.co.uk>
Tue, 3 Oct 2017 20:34:51 +0000 (21:34 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Wed, 4 Oct 2017 16:52:46 +0000 (17:52 +0100)
In the next few patches, we wish to enable different features for the
scheduler, some which may subtlety change ABI (e.g. allow requests to be
reordered under different circumstances). So we need to make sure
userspace is cognizant of the changes (if they care), by which we employ
the usual method of a GETPARAM. We already have an
I915_PARAM_HAS_SCHEDULER (which notes the existing ability to reorder
requests to avoid bubbles), and now we wish to extend that to be a
bitmask to describe the different capabilities implemented.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171003203453.15692-7-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_drv.c
include/uapi/drm/i915_drm.h

index 74a456fe487f46d3fb8a76fdc9412a7f8a6a28d3..00633280570226ca255296503d1463739e1ab71d 100644 (file)
@@ -367,8 +367,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
                value = i915_gem_mmap_gtt_version();
                break;
        case I915_PARAM_HAS_SCHEDULER:
-               value = dev_priv->engine[RCS] &&
-                       dev_priv->engine[RCS]->schedule;
+               value = 0;
+               if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule)
+                       value |= I915_SCHEDULER_CAP_ENABLED;
                break;
        case I915_PARAM_MMAP_VERSION:
                /* Remember to bump this if the version changes! */
index fe25a01c81f22661cb5c8a7d3db34a7851e579b3..aa4a3b20ef6b8b4dd58a2e251d8a7c72357af410 100644 (file)
@@ -397,10 +397,17 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_MIN_EU_IN_POOL       39
 #define I915_PARAM_MMAP_GTT_VERSION     40
 
-/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
  * priorities and the driver will attempt to execute batches in priority order.
+ * The param returns a capability bitmask, nonzero implies that the scheduler
+ * is enabled, with different features present according to the mask.
  */
 #define I915_PARAM_HAS_SCHEDULER        41
+#define   I915_SCHEDULER_CAP_ENABLED   (1ul << 0)
+#define   I915_SCHEDULER_CAP_PRIORITY  (1ul << 1)
+#define   I915_SCHEDULER_CAP_PREEMPTION        (1ul << 2)
+
 #define I915_PARAM_HUC_STATUS           42
 
 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of