static int imx6_pcie_wait_for_link(struct pcie_port *pp)
{
-- ---- int count = 200;
++ ++++ unsigned int retries;
-- ---- while (!dw_pcie_link_up(pp)) {
++ ++++ for (retries = 0; retries < 200; retries++) {
++ ++++ if (dw_pcie_link_up(pp))
++ ++++ return 0;
usleep_range(100, 1000);
-- ---- if (--count)
-- ---- continue;
-- ----
-- ---- dev_err(pp->dev, "phy link never came up\n");
-- ---- dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
-- ---- readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
-- ---- readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
-- ---- return -EINVAL;
}
-- ---- return 0;
++ ++++ dev_err(pp->dev, "phy link never came up\n");
++ ++++ dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
++ ++++ readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
++ ++++ readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
++ ++++ return -EINVAL;
++ + ++}
++ + ++
++++ ++static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
++++ ++{
++++ ++ u32 tmp;
++++ ++ unsigned int retries;
++++ ++
++++ ++ for (retries = 0; retries < 200; retries++) {
++++ ++ tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
++++ ++ /* Test if the speed change finished. */
++++ ++ if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
++++ ++ return 0;
++++ ++ usleep_range(100, 1000);
++++ ++ }
++++ ++
++++ ++ dev_err(pp->dev, "Speed change timeout\n");
++++ ++ return -EINVAL;
+ }
+
static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
{
struct pcie_port *pp = arg;
return dw_handle_msi_irq(pp);
}
-- ----static int imx6_pcie_start_link(struct pcie_port *pp)
++ ++++static int imx6_pcie_establish_link(struct pcie_port *pp)
{
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
---- -- uint32_t tmp;
---- -- int ret, count;
++++ ++ u32 tmp;
++++ ++ int ret;
/*
* Force Gen1 operation when starting the link. In case the link is