drm/i915/guc: reserve the doorbell before selecting the cacheline
authorDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Mon, 22 Oct 2018 23:04:23 +0000 (16:04 -0700)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 23 Oct 2018 08:36:52 +0000 (09:36 +0100)
Cacheline selection is only needed if we actually manage to reserve a
doorbell.

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20181022230427.5616-2-daniele.ceraolospurio@intel.com
drivers/gpu/drm/i915/intel_guc_submission.c

index b089e5283307aed85527e186a161672ca02915cb..8c3b5a9facee8b24578f6a193fc048da3ce9f305 100644 (file)
@@ -955,6 +955,10 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
        }
        client->vaddr = vaddr;
 
+       ret = reserve_doorbell(client);
+       if (ret)
+               goto err_vaddr;
+
        client->doorbell_offset = __select_cacheline(guc);
 
        /*
@@ -967,10 +971,6 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
        else
                client->proc_desc_offset = (GUC_DB_SIZE / 2);
 
-       ret = reserve_doorbell(client);
-       if (ret)
-               goto err_vaddr;
-
        DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
                         priority, client, client->engines, client->stage_id);
        DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",