MIPS: BMIPS: BMIPS5000 has I cache filing from D cache
authorFlorian Fainelli <f.fainelli@gmail.com>
Mon, 4 Apr 2016 17:55:34 +0000 (10:55 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 13 May 2016 12:02:06 +0000 (14:02 +0200)
BMIPS5000 and BMIPS52000 processors have their I-cache filling from the
D-cache. Since BMIPS_GENERIC does not provide (yet) a
cpu-feature-overrides.h file, this was not set anywhere, so make sure
the R4K cache detection takes care of that.

Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13010/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/c-r4k.c

index e64d595fdcf2c9a9b49c8fcefb7070c29cd07a91..92e54fbdbf9616ef380e7d8665ce4509add34075 100644 (file)
@@ -1317,6 +1317,10 @@ static void probe_pcache(void)
                c->icache.flags |= MIPS_CACHE_IC_F_DC;
                break;
 
+       case CPU_BMIPS5000:
+               c->icache.flags |= MIPS_CACHE_IC_F_DC;
+               break;
+
        case CPU_LOONGSON2:
                /*
                 * LOONGSON2 has 4 way icache, but when using indexed cache op,