Move the asic specific code into the IP modules.
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Common GART table functions.
*/
-/**
- * amdgpu_gart_set_defaults - set the default gart_size
- *
- * @adev: amdgpu_device pointer
- *
- * Set the default gart_size based on parameters and available VRAM.
- */
-void amdgpu_gart_set_defaults(struct amdgpu_device *adev)
-{
- u64 gart_size;
-
- if (amdgpu_gart_size == -1) {
- switch (adev->asic_type) {
-#ifdef CONFIG_DRM_AMDGPU_SI
- case CHIP_HAINAN: /* no MM engines */
-#endif
- case CHIP_TOPAZ: /* no MM engines */
- case CHIP_POLARIS11: /* all engines support GPUVM */
- case CHIP_POLARIS10: /* all engines support GPUVM */
- case CHIP_POLARIS12: /* all engines support GPUVM */
- case CHIP_VEGA10: /* all engines support GPUVM */
- default:
- gart_size = 256;
- break;
-#ifdef CONFIG_DRM_AMDGPU_SI
- case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
- case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
- case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
- case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
-#endif
-#ifdef CONFIG_DRM_AMDGPU_CIK
- case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
- case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
- case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
- case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
- case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
-#endif
- case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
- case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
- case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
- case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
- case CHIP_RAVEN: /* DCE SG support */
- gart_size = 1024;
- break;
- }
- } else {
- gart_size = amdgpu_gart_size;
- }
-
- adev->mc.gart_size = gart_size << 20;
-}
-
/**
* amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
*
const struct amdgpu_gart_funcs *gart_funcs;
};
-void amdgpu_gart_set_defaults(struct amdgpu_device *adev);
int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
adev->mc.visible_vram_size = adev->mc.aper_size;
- amdgpu_gart_set_defaults(adev);
+ /* set the gart size */
+ if (amdgpu_gart_size == -1) {
+ switch (adev->asic_type) {
+ case CHIP_HAINAN: /* no MM engines */
+ default:
+ adev->mc.gart_size = 256ULL << 20;
+ break;
+ case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
+ case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
+ case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
+ case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
+ adev->mc.gart_size = 1024ULL << 20;
+ break;
+ }
+ } else {
+ adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+ }
+
gmc_v6_0_vram_gtt_location(adev, &adev->mc);
return 0;
if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
adev->mc.visible_vram_size = adev->mc.real_vram_size;
- amdgpu_gart_set_defaults(adev);
+ /* set the gart size */
+ if (amdgpu_gart_size == -1) {
+ switch (adev->asic_type) {
+ case CHIP_TOPAZ: /* no MM engines */
+ default:
+ adev->mc.gart_size = 256ULL << 20;
+ break;
+#ifdef CONFIG_DRM_AMDGPU_CIK
+ case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
+ case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
+ case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
+ case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
+ case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
+ adev->mc.gart_size = 1024ULL << 20;
+ break;
+#endif
+ }
+ } else {
+ adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+ }
+
gmc_v7_0_vram_gtt_location(adev, &adev->mc);
return 0;
if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
adev->mc.visible_vram_size = adev->mc.real_vram_size;
- amdgpu_gart_set_defaults(adev);
+ /* set the gart size */
+ if (amdgpu_gart_size == -1) {
+ switch (adev->asic_type) {
+ case CHIP_POLARIS11: /* all engines support GPUVM */
+ case CHIP_POLARIS10: /* all engines support GPUVM */
+ case CHIP_POLARIS12: /* all engines support GPUVM */
+ default:
+ adev->mc.gart_size = 256ULL << 20;
+ break;
+ case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
+ case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
+ case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
+ case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
+ adev->mc.gart_size = 1024ULL << 20;
+ break;
+ }
+ } else {
+ adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+ }
+
gmc_v8_0_vram_gtt_location(adev, &adev->mc);
return 0;
if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
adev->mc.visible_vram_size = adev->mc.real_vram_size;
- amdgpu_gart_set_defaults(adev);
+ /* set the gart size */
+ if (amdgpu_gart_size == -1) {
+ switch (adev->asic_type) {
+ case CHIP_VEGA10: /* all engines support GPUVM */
+ default:
+ adev->mc.gart_size = 256ULL << 20;
+ break;
+ case CHIP_RAVEN: /* DCE SG support */
+ adev->mc.gart_size = 1024ULL << 20;
+ break;
+ }
+ } else {
+ adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
+ }
+
gmc_v9_0_vram_gtt_location(adev, &adev->mc);
return 0;