drm/amdgpu: enable AGP aperture for GMC9 v2

Enable the old AGP aperture to avoid GART mappings.

v2: don't enable it for SRIOV

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 3403ded39d13c01f678106b0cc15dc319e2038e7..ffd0ec9586d1d090daf96aefa6b5e0fcafbb6510 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -65,16 +65,16 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 {
        uint64_t value;
 
-       /* Disable AGP. */
+       /* Program the AGP BAR */
        WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
-       WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
-       WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF);
+       WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+       WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
        /* Program the system aperture low logical page number. */
        WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-                    adev->gmc.vram_start >> 18);
+                    min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
        WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-                    adev->gmc.vram_end >> 18);
+                    max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
 
        /* Set default page address. */
        value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index f467638eb49da305c8c2555d99e57e30acb84cc3..3529c55ab52dcbda3139e654ffde7a1d9245a39a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -772,6 +772,8 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
                base = mmhub_v1_0_get_fb_location(adev);
        amdgpu_gmc_vram_location(adev, &adev->gmc, base);
        amdgpu_gmc_gart_location(adev, mc);
+       if (!amdgpu_sriov_vf(adev))
+               amdgpu_gmc_agp_location(adev, mc);
        /* base offset of vram pages */
        adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 5f6a9c85488f211852db9c4eae3cf7e2105959d8..73d7c075dd33b7a16e0473229adebf8dbc53cf5c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -76,16 +76,16 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
        uint64_t value;
        uint32_t tmp;
 
-       /* Disable AGP. */
+       /* Program the AGP BAR */
        WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
-       WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
-       WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
+       WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+       WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
        /* Program the system aperture low logical page number. */
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-                    adev->gmc.vram_start >> 18);
+                    min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-                    adev->gmc.vram_end >> 18);
+                    max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
 
        /* Set default page address. */
        value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +