net: stmmac: dwmac-rk: Fix clk rate when provided by soc

The first iteration of the dwmac-rk support did access an intermediate
clock directly below the pll selector. This was removed in a subsequent
revision, but the clock and one invocation remained. This results in
the driver trying to set the rate of a non-existent clock when the soc
and not some external source provides the phy clock for RMII phys.

So set the rate of the correct clock and remove the remaining now
completely unused definition.

Fixes: 436f5ae08f9d ("GMAC: add driver for Rockchip RK3288 SoCs integrated GMAC")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index a39607085281b141c86501e3c7125b34612a7caa..5dafebb94fa4c98a905e75f6a0f26301bc030099 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -42,7 +42,6 @@ struct rk_priv_data {
        bool clock_input;
 
        struct clk *clk_mac;
-       struct clk *clk_mac_pll;
        struct clk *gmac_clkin;
        struct clk *mac_clk_rx;
        struct clk *mac_clk_tx;
@@ -209,7 +208,7 @@ static int gmac_clk_init(struct rk_priv_data *bsp_priv)
                dev_info(dev, "clock input from PHY\n");
        } else {
                if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
-                       clk_set_rate(bsp_priv->clk_mac_pll, 50000000);
+                       clk_set_rate(bsp_priv->clk_mac, 50000000);
        }
 
        return 0;