arm64: sysreg: add performance monitor registers

This patch adds sysreg definitions for system registers which are part
of the performance monitors extension. Subsequent patches will make use
of these definitions.

The set of registers is described in ARM DDI 0487A.k_iss10775, Table
D5-9. The encodings were taken from Table C5-6 in the same document.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b54f8a401664fa235c76d4c10b739ae94ab3f709..3498d02b29d9c3f5f9b3478ffd2d4b450ea1fb94 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -149,11 +149,36 @@
 #define SYS_ID_AA64MMFR1_EL1           sys_reg(3, 0, 0, 7, 1)
 #define SYS_ID_AA64MMFR2_EL1           sys_reg(3, 0, 0, 7, 2)
 
+#define SYS_PMINTENSET_EL1             sys_reg(3, 0, 9, 14, 1)
+#define SYS_PMINTENCLR_EL1             sys_reg(3, 0, 9, 14, 2)
+
 #define SYS_CTR_EL0                    sys_reg(3, 3, 0, 0, 1)
 #define SYS_DCZID_EL0                  sys_reg(3, 3, 0, 0, 7)
 
+#define SYS_PMCR_EL0                   sys_reg(3, 3, 9, 12, 0)
+#define SYS_PMCNTENSET_EL0             sys_reg(3, 3, 9, 12, 1)
+#define SYS_PMCNTENCLR_EL0             sys_reg(3, 3, 9, 12, 2)
+#define SYS_PMOVSCLR_EL0               sys_reg(3, 3, 9, 12, 3)
+#define SYS_PMSWINC_EL0                        sys_reg(3, 3, 9, 12, 4)
+#define SYS_PMSELR_EL0                 sys_reg(3, 3, 9, 12, 5)
+#define SYS_PMCEID0_EL0                        sys_reg(3, 3, 9, 12, 6)
+#define SYS_PMCEID1_EL0                        sys_reg(3, 3, 9, 12, 7)
+#define SYS_PMCCNTR_EL0                        sys_reg(3, 3, 9, 13, 0)
+#define SYS_PMXEVTYPER_EL0             sys_reg(3, 3, 9, 13, 1)
+#define SYS_PMXEVCNTR_EL0              sys_reg(3, 3, 9, 13, 2)
+#define SYS_PMUSERENR_EL0              sys_reg(3, 3, 9, 14, 0)
+#define SYS_PMOVSSET_EL0               sys_reg(3, 3, 9, 14, 3)
+
 #define SYS_CNTFRQ_EL0                 sys_reg(3, 3, 14, 0, 0)
 
+#define __PMEV_op2(n)                  ((n) & 0x7)
+#define __CNTR_CRm(n)                  (0x8 | (((n) >> 3) & 0x3))
+#define SYS_PMEVCNTRn_EL0(n)           sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
+#define __TYPER_CRm(n)                 (0xc | (((n) >> 3) & 0x3))
+#define SYS_PMEVTYPERn_EL0(n)          sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
+
+#define SYS_PMCCFILTR_EL0              sys_reg (3, 3, 14, 15, 7)
+
 /* Common SCTLR_ELx flags. */
 #define SCTLR_ELx_EE    (1 << 25)
 #define SCTLR_ELx_I    (1 << 12)