drm/i915: Extract intel_get_cagf

Code to be shared between debugfs and the PMU implementation.

v2: Checkpatch cleanup.
v3: Also consolidate i915_sysfs.c/gt_act_freq_mhz_show.
v4: Rebase.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-1-tvrtko.ursulin@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 41d49a4d25d352fe27f7a7fbcc0318c1dcfdf0d6..28294470ae31f2275a6b984810d6ebb206d5a6e0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1151,13 +1151,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
                rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
                rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
-               if (INTEL_GEN(dev_priv) >= 9)
-                       cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
-               else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-                       cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
-               else
-                       cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
-               cagf = intel_gpu_freq(dev_priv, cagf);
+               cagf = intel_gpu_freq(dev_priv,
+                                     intel_get_cagf(dev_priv, rpstat));
 
                intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9a890f6ad2df5ae0a2c0c211a19ef605e8a14776..019117144b3bc96ece3ec20d097be675c6cd2ec3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4226,6 +4226,8 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
                           const i915_reg_t reg);
 
+u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
+
 #define I915_READ8(reg)                dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
 #define I915_WRITE8(reg, val)  dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
 

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 791759f632e1dd65cde71891c0db6177281ea0e9..450ac7d343ad89088c1169c3acf879dda9ca88ca 100644 (file)
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -252,14 +252,9 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
                freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
                ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
        } else {
-               u32 rpstat = I915_READ(GEN6_RPSTAT1);
-               if (INTEL_GEN(dev_priv) >= 9)
-                       ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
-               else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-                       ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
-               else
-                       ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
-               ret = intel_gpu_freq(dev_priv, ret);
+               ret = intel_gpu_freq(dev_priv,
+                                    intel_get_cagf(dev_priv,
+                                                   I915_READ(GEN6_RPSTAT1)));
        }
        mutex_unlock(&dev_priv->pcu_lock);
 

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e445ec17483178fcc3bcdea41a06e42e0c90a9f1..f1dc36c1fd697eaa6269cf9ce4e46d723948a7d7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9468,3 +9468,17 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
        intel_runtime_pm_put(dev_priv);
        return DIV_ROUND_UP_ULL(time_hw * units, div);
 }
+
+u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
+{
+       u32 cagf;
+
+       if (INTEL_GEN(dev_priv) >= 9)
+               cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+       else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+               cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
+       else
+               cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
+
+       return  cagf;
+}