clk: mediatek: mt8183: Register 13MHz clock earlier for clocksource

The 13MHz clock should be registered before clocksource driver is
initialized. Use CLK_OF_DECLARE_DRIVER() to guarantee.

Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support")
Cc: <stable@vger.kernel.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 1aa5f40592514db3e015c67e176d43c44ce22a69..73b7e238eee75e020373b98e3727277676920c21 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -25,9 +25,11 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
        FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
 };
 
+static const struct mtk_fixed_factor top_early_divs[] = {
+       FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
+};
+
 static const struct mtk_fixed_factor top_divs[] = {
-       FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1,
-               2),
        FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
                2),
        FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
@@ -1148,37 +1150,57 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
        return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 }
 
+static struct clk_onecell_data *top_clk_data;
+
+static void clk_mt8183_top_init_early(struct device_node *node)
+{
+       int i;
+
+       top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+       for (i = 0; i < CLK_TOP_NR_CLK; i++)
+               top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
+
+       mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+                       top_clk_data);
+
+       of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
+}
+
+CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
+                       clk_mt8183_top_init_early);
+
 static int clk_mt8183_top_probe(struct platform_device *pdev)
 {
        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        void __iomem *base;
-       struct clk_onecell_data *clk_data;
        struct device_node *node = pdev->dev.of_node;
 
        base = devm_ioremap_resource(&pdev->dev, res);
        if (IS_ERR(base))
                return PTR_ERR(base);
 
-       clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
-
        mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-               clk_data);
+               top_clk_data);
+
+       mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+               top_clk_data);
 
-       mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+       mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
 
        mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
-               node, &mt8183_clk_lock, clk_data);
+               node, &mt8183_clk_lock, top_clk_data);
 
        mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
-               base, &mt8183_clk_lock, clk_data);
+               base, &mt8183_clk_lock, top_clk_data);
 
        mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
-               base, &mt8183_clk_lock, clk_data);
+               base, &mt8183_clk_lock, top_clk_data);
 
        mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
-               clk_data);
+               top_clk_data);
 
-       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+       return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
 }
 
 static int clk_mt8183_infra_probe(struct platform_device *pdev)