OMAP3 clock: add a short delay when lowering CORE clk rate

When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 5458ab3bf65a69df311ff1ec387f4d93591f6093..4bfa650bb34b57a814cc4f49b67463398a060fc9 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = {
 
 #define MIN_SDRC_DLL_LOCK_FREQ         83000000
 
+#define CYCLES_PER_MHZ                 1000000
+
+/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
+#define SDRC_MPURATE_SCALE             8
+
+/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
+#define SDRC_MPURATE_BASE_SHIFT                9
+
+/*
+ * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
+ * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
+ */
+#define SDRC_MPURATE_LOOPS             96
+
 /**
  * omap3_dpll_recalc - recalculate DPLL rate
  * @clk: DPLL struct clk
@@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 {
        u32 new_div = 0;
        u32 unlock_dll = 0;
-       unsigned long validrate, sdrcrate;
+       u32 c;
+       unsigned long validrate, sdrcrate, mpurate;
        struct omap_sdrc_params *sp;
 
        if (!clk || !rate)
@@ -737,6 +752,17 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
                unlock_dll = 1;
        }
 
+       /*
+        * XXX This only needs to be done when the CPU frequency changes
+        */
+       mpurate = arm_fck.rate / CYCLES_PER_MHZ;
+       c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+       c += 1;  /* for safety */
+       c *= SDRC_MPURATE_LOOPS;
+       c >>= SDRC_MPURATE_SCALE;
+       if (c == 0)
+               c = 1;
+
        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
                 validrate);
        pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
@@ -747,7 +773,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
        /* REVISIT: Add SDRC_MR changing to this code also */
        omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-                                 sp->actim_ctrlb, new_div, unlock_dll);
+                                 sp->actim_ctrlb, new_div, unlock_dll, c);
 
        return 0;
 }

diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 84781a6cd26371ca30c1e3d6f99abb414d339944..8d4a88c307180cffff3a4cec230fe4152297d064 100644 (file)
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -42,10 +42,14 @@
  * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
  * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
  *      SDRC rates < 83MHz
+ * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *      reprogramming the SDRC when switching to a slower MPU speed
+ *
  */
 ENTRY(omap3_sram_configure_core_dpll)
        stmfd   sp!, {r1-r12, lr}       @ store regs to stack
        ldr     r4, [sp, #52]           @ pull extra args off the stack
+       ldr     r5, [sp, #56]           @ load extra args from the stack
        dsb                             @ flush buffered writes to interconnect
        cmp     r3, #0x2
        blne    configure_sdrc
@@ -59,7 +63,11 @@ ENTRY(omap3_sram_configure_core_dpll)
        bleq    wait_dll_unlock
        blne    wait_dll_lock
        cmp     r3, #0x1
-       blne    configure_sdrc
+       beq     return_to_sdram
+       bl      configure_sdrc
+       mov     r12, r5                 @ if slowing, wait for SDRC to stabilize
+       bl      wait_clk_stable
+return_to_sdram:
        isb                             @ prevent speculative exec past here
        mov     r0, #0                  @ return value
        ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
@@ -106,16 +114,6 @@ configure_core_dpll:
 wait_clk_stable:
        subs    r12, r12, #1
        bne     wait_clk_stable
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
        bx      lr
 enable_sdrc:
        ldr     r11, omap3_cm_iclken1_core

diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index dca7c16ae903726a6937ca6a79d7e5d8791fddaa..c32fa0a220dccd405fa910efa1273b049e2b09be 100644 (file)
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
                                     u32 sdrc_actim_ctrla,
                                     u32 sdrc_actim_ctrlb, u32 m2,
-                                    u32 unlock_dll);
+                                    u32 unlock_dll, u32 f);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
                                          u32 sdrc_actim_ctrla,
                                          u32 sdrc_actim_ctrlb, u32 m2,
-                                         u32 unlock_dll);
+                                         u32 unlock_dll, u32 f);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #endif

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a5b9bcd6b10821c5ad38166e0600c5ceba924fb5..79c0f02544267761c60976728935046737dd1134 100644 (file)
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void)
 static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
                                              u32 sdrc_actim_ctrla,
                                              u32 sdrc_actim_ctrlb,
-                                             u32 m2, u32 unlock_dll);
+                                             u32 m2, u32 unlock_dll,
+                                             u32 f);
 u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-                             u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
+                             u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
+                             u32 f)
 {
        BUG_ON(!_omap3_sram_configure_core_dpll);
        return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
                                               sdrc_actim_ctrla,
                                               sdrc_actim_ctrlb, m2,
-                                              unlock_dll);
+                                              unlock_dll, f);
 }
 
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */