drivers: net: xgene: Add rx_overrun/tx_underrun statistics
authorIyappan Subramanian <isubramanian@apm.com>
Wed, 10 May 2017 20:45:06 +0000 (13:45 -0700)
committerDavid S. Miller <davem@davemloft.net>
Tue, 16 May 2017 15:41:10 +0000 (11:41 -0400)
This patch adds rx_overrun and tx_underrun ethtool statistic counters.

Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c
drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
drivers/net/ethernet/apm/xgene/xgene_enet_main.h
drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c
drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h

index a7eed3b83912612d4b5f3d0f521ede1478c82833..6b2a4b917c1094600bc9c24656b8f40af8744720 100644 (file)
@@ -71,6 +71,7 @@ static const struct xgene_gstrings_stats gstrings_extd_stats[] = {
        XGENE_EXTD_STAT(rx_fragments_cntr, RFRG, 16),
        XGENE_EXTD_STAT(rx_jabber_cntr, RJBR, 16),
        XGENE_EXTD_STAT(rx_dropped_pkt_cntr, RDRP, 16),
+       XGENE_EXTD_STAT(rx_overrun_cntr, DUMP, 0),
        XGENE_EXTD_STAT(tx_multicast_pkt_cntr, TMCA, 31),
        XGENE_EXTD_STAT(tx_broadcast_pkt_cntr, TBCA, 31),
        XGENE_EXTD_STAT(tx_pause_ctrl_frame_cntr, TXPF, 16),
@@ -88,11 +89,14 @@ static const struct xgene_gstrings_stats gstrings_extd_stats[] = {
        XGENE_EXTD_STAT(tx_ctrl_frame_cntr, TXCF, 12),
        XGENE_EXTD_STAT(tx_oversize_frame_cntr, TOVR, 12),
        XGENE_EXTD_STAT(tx_undersize_frame_cntr, TUND, 12),
-       XGENE_EXTD_STAT(tx_fragments_cntr, TFRG, 12)
+       XGENE_EXTD_STAT(tx_fragments_cntr, TFRG, 12),
+       XGENE_EXTD_STAT(tx_underrun_cntr, DUMP, 0)
 };
 
 #define XGENE_STATS_LEN                ARRAY_SIZE(gstrings_stats)
 #define XGENE_EXTD_STATS_LEN   ARRAY_SIZE(gstrings_extd_stats)
+#define RX_OVERRUN_IDX         22
+#define TX_UNDERRUN_IDX                41
 
 static void xgene_get_drvinfo(struct net_device *ndev,
                              struct ethtool_drvinfo *info)
@@ -211,14 +215,20 @@ static int xgene_get_sset_count(struct net_device *ndev, int sset)
 
 static void xgene_get_extd_stats(struct xgene_enet_pdata *pdata)
 {
+       u32 rx_drop, tx_drop;
        u32 tmp;
        int i;
 
        for (i = 0; i < XGENE_EXTD_STATS_LEN; i++) {
                tmp = xgene_enet_rd_stat(pdata, gstrings_extd_stats[i].addr);
-               pdata->extd_stats[i] += tmp &
-                       GENMASK(gstrings_extd_stats[i].mask - 1, 0);
+               if (gstrings_extd_stats[i].mask)
+                       pdata->extd_stats[i] += tmp &
+                               GENMASK(gstrings_extd_stats[i].mask - 1, 0);
        }
+
+       pdata->mac_ops->get_drop_cnt(pdata, &rx_drop, &tx_drop);
+       pdata->extd_stats[RX_OVERRUN_IDX] += rx_drop;
+       pdata->extd_stats[TX_UNDERRUN_IDX] += tx_drop;
 }
 
 int xgene_extd_stats_init(struct xgene_enet_pdata *pdata)
index 9e891939fcf88e7fa49a649022383121a12d8b28..5278d62d5b57c8cf6ae65f06f60b2f00d36c1e41 100644 (file)
@@ -618,6 +618,16 @@ static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
        xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
 }
 
+static void xgene_gmac_get_drop_cnt(struct xgene_enet_pdata *pdata,
+                                   u32 *rx, u32 *tx)
+{
+       u32 count;
+
+       xgene_enet_rd_mcx_csr(pdata, ICM_ECM_DROP_COUNT_REG0_ADDR, &count);
+       *rx = ICM_DROP_COUNT(count);
+       *tx = ECM_DROP_COUNT(count);
+}
+
 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
 {
        u32 val = 0xffffffff;
@@ -1027,6 +1037,7 @@ const struct xgene_mac_ops xgene_gmac_ops = {
        .tx_enable = xgene_gmac_tx_enable,
        .rx_disable = xgene_gmac_rx_disable,
        .tx_disable = xgene_gmac_tx_disable,
+       .get_drop_cnt = xgene_gmac_get_drop_cnt,
        .set_speed = xgene_gmac_set_speed,
        .set_mac_addr = xgene_gmac_set_mac_addr,
        .set_framesize = xgene_enet_set_frame_size,
index f1a4cfa641ae25f98254630539f986676171c9e8..5d3e18d3c94c252d74b80a7e70eecde37a9eff6a 100644 (file)
@@ -192,6 +192,10 @@ enum xgene_enet_rm {
 #define CFG_CLE_NXTFPSEL0(val)         (((val) << 20) & GENMASK(23, 20))
 #define ICM_CONFIG0_REG_0_ADDR         0x0400
 #define ICM_CONFIG2_REG_0_ADDR         0x0410
+#define ECM_CONFIG0_REG_0_ADDR         0x0500
+#define ECM_CONFIG0_REG_1_ADDR         0x0504
+#define ICM_ECM_DROP_COUNT_REG0_ADDR   0x0508
+#define ICM_ECM_DROP_COUNT_REG1_ADDR   0x050c
 #define RX_DV_GATE_REG_0_ADDR          0x05fc
 #define TX_DV_GATE_EN0                 BIT(2)
 #define RX_DV_GATE_EN0                 BIT(1)
@@ -267,6 +271,10 @@ enum xgene_enet_rm {
 #define TOVR_ADDR      0x49
 #define TUND_ADDR      0x4a
 #define TFRG_ADDR      0x4b
+#define DUMP_ADDR      0x27
+
+#define ECM_DROP_COUNT(src)    xgene_get_bits(src, 0, 15)
+#define ICM_DROP_COUNT(src)    xgene_get_bits(src, 16, 31)
 
 #define TSO_IPPROTO_TCP                        1
 
index cbdc09c1d0d733b2b1ac0bfaf490a689914db351..cabe54edb17c97ec3498b3c1a790852e050b4283 100644 (file)
@@ -157,6 +157,7 @@ struct xgene_mac_ops {
        void (*rx_enable)(struct xgene_enet_pdata *pdata);
        void (*tx_disable)(struct xgene_enet_pdata *pdata);
        void (*rx_disable)(struct xgene_enet_pdata *pdata);
+       void (*get_drop_cnt)(struct xgene_enet_pdata *pdata, u32 *rx, u32 *tx);
        void (*set_speed)(struct xgene_enet_pdata *pdata);
        void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
        void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize);
index cb6350f7e137add88831b9837a72fdc094f8e2c4..2919d3e36fada99dcfa1d98382b1d929969dd5cd 100644 (file)
@@ -95,6 +95,19 @@ static int xgene_enet_ecc_init(struct xgene_enet_pdata *p)
        return -ENODEV;
 }
 
+static void xgene_sgmac_get_drop_cnt(struct xgene_enet_pdata *pdata,
+                                    u32 *rx, u32 *tx)
+{
+       u32 addr, count;
+
+       addr = (pdata->enet_id != XGENE_ENET1) ?
+               XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR :
+               ICM_ECM_DROP_COUNT_REG0_ADDR + pdata->port_id * OFFSET_4;
+       count = xgene_enet_rd_mcx_csr(pdata, addr);
+       *rx = ICM_DROP_COUNT(count);
+       *tx = ECM_DROP_COUNT(count);
+}
+
 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p)
 {
        u32 val;
@@ -600,6 +613,7 @@ const struct xgene_mac_ops xgene_sgmac_ops = {
        .tx_enable      = xgene_sgmac_tx_enable,
        .rx_disable     = xgene_sgmac_rx_disable,
        .tx_disable     = xgene_sgmac_tx_disable,
+       .get_drop_cnt   = xgene_sgmac_get_drop_cnt,
        .set_speed      = xgene_sgmac_set_speed,
        .set_mac_addr   = xgene_sgmac_set_mac_addr,
        .set_framesize  = xgene_sgmac_set_frame_size,
index c6a5dac3a126cfff6fae6f1d70df2cd6e3671f94..56dff380cbb7ac7e84687be2919a29f07b0e10c9 100644 (file)
@@ -180,6 +180,16 @@ static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
        return 0;
 }
 
+static void xgene_xgmac_get_drop_cnt(struct xgene_enet_pdata *pdata,
+                                    u32 *rx, u32 *tx)
+{
+       u32 count;
+
+       xgene_enet_rd_axg_csr(pdata, XGENET_ICM_ECM_DROP_COUNT_REG0, &count);
+       *rx = ICM_DROP_COUNT(count);
+       *tx = ECM_DROP_COUNT(count);
+}
+
 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
 {
        xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);
@@ -537,6 +547,7 @@ const struct xgene_mac_ops xgene_xgmac_ops = {
        .set_mac_addr = xgene_xgmac_set_mac_addr,
        .set_framesize = xgene_xgmac_set_frame_size,
        .set_mss = xgene_xgmac_set_mss,
+       .get_drop_cnt = xgene_xgmac_get_drop_cnt,
        .link_state = xgene_enet_link_state,
        .enable_tx_pause = xgene_xgmac_enable_tx_pause,
        .flowctl_rx = xgene_xgmac_flowctl_rx,
index 9b98c83951a3823ce74a72c4d1475d0a6b91c6bb..a3b45517df452599402e0700bb8adf15da727314 100644 (file)
@@ -71,6 +71,8 @@
 #define XG_RSIF_CONFIG1_REG_ADDR       0x00b8
 #define XG_RSIF_PLC_CLE_BUFF_THRESH    0x1
 #define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)
+#define XG_MCX_ECM_CONFIG0_REG_0_ADDR          0x0070
+#define XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR    0x0124
 #define XCLE_BYPASS_REG0_ADDR           0x0160
 #define XCLE_BYPASS_REG1_ADDR           0x0164
 #define XG_CFG_BYPASS_ADDR             0x0204
@@ -81,6 +83,8 @@
 #define XG_ENET_SPARE_CFG_REG_ADDR     0x040c
 #define XG_ENET_SPARE_CFG_REG_1_ADDR   0x0410
 #define XGENET_RX_DV_GATE_REG_0_ADDR   0x0804
+#define XGENET_ECM_CONFIG0_REG_0       0x0870
+#define XGENET_ICM_ECM_DROP_COUNT_REG0 0x0924
 #define XGENET_CSR_ECM_CFG_0_ADDR      0x0880
 #define XGENET_CSR_MULTI_DPF0_ADDR     0x0888
 #define XGENET_CSR_MULTI_DPF1_ADDR     0x088c