AcpiDisplayType_DFP6 = 12
};
-enum dm_pp_power_level {
- DM_PP_POWER_LEVEL_INVALID,
- DM_PP_POWER_LEVEL_ULTRA_LOW,
- DM_PP_POWER_LEVEL_LOW,
- DM_PP_POWER_LEVEL_NOMINAL,
- DM_PP_POWER_LEVEL_PERFORMANCE,
-
- DM_PP_POWER_LEVEL_0 = DM_PP_POWER_LEVEL_ULTRA_LOW,
- DM_PP_POWER_LEVEL_1 = DM_PP_POWER_LEVEL_LOW,
- DM_PP_POWER_LEVEL_2 = DM_PP_POWER_LEVEL_NOMINAL,
- DM_PP_POWER_LEVEL_3 = DM_PP_POWER_LEVEL_PERFORMANCE,
- DM_PP_POWER_LEVEL_4 = DM_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
- DM_PP_POWER_LEVEL_5 = DM_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
- DM_PP_POWER_LEVEL_6 = DM_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
- DM_PP_POWER_LEVEL_7 = DM_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
-};
-
struct dm_pp_power_level_change_request {
- enum dm_pp_power_level power_level;
+ enum dm_pp_clocks_state power_level;
};
struct dm_pp_clock_for_voltage_req {