This extra clock is needed to access the registers of the harware RNG
used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as
well as in the driver): "hwrng: omap - Fix clock resource by adding a
register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
"inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 25>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(clk) 1 25>,
+ <&CP110_LABEL(clk) 1 17>;
status = "okay";
};