drm/i915/skl: Updated the gen6_init_rps_frequencies function

On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
function for SKL, to store the frequency values as per the actual hardware unit.

v2: Corrected the conversion from 50 to 16.66 MHZ (Ville)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c0901ec47bcf02ba63886a78bf0e5c8b16d19751..f240e8578e00e72c2b91b9c97fc9c3e78f7e201b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4181,6 +4181,13 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
        dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
        dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
        dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
+       if (IS_SKYLAKE(dev)) {
+               /* Store the frequency values in 16.66 MHZ units, which is
+                  the natural hardware unit for SKL */
+               dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
+               dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
+               dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
+       }
        /* hw_max = RP0 until we check for overclocking */
        dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;