ixp4xx: add a second UART to the core DTS

The ixp family provides two UARTs, the first is designated
as a high-speed one, the second is designated as the console. Boards
vary in which one they use as the console.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>

diff --git a/target/linux/ixp4xx/patches-5.10/140-ARM-dts-ixp4xx-add-second-uart.patch b/target/linux/ixp4xx/patches-5.10/140-ARM-dts-ixp4xx-add-second-uart.patch
new file mode 100644 (file)
index 0000000..0d9b0d0
--- /dev/null
+++ b/target/linux/ixp4xx/patches-5.10/140-ARM-dts-ixp4xx-add-second-uart.patch
@@ -0,0 +1,26 @@
+diff -ruN a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts
+diff -ruN a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
+--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi      2021-05-19 16:16:30.448864696 +0200
++++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi      2021-05-19 14:50:52.447176661 +0200
+@@ -70,6 +70,20 @@
+                       no-loopback-test;
+               };
+ 
++              uart1: serial@c8001000 {
++                      compatible = "intel,xscale-uart";
++                      reg = <0xc8001000 0x1000>;
++                      /*
++                       * The reg-offset and reg-shift is a side effect
++                       * of running the platform in big endian mode.
++                       */
++                      reg-offset = <3>;
++                      reg-shift = <2>;
++                      interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
++                      clock-frequency = <14745600>;
++                      no-loopback-test;
++              };
++
+               gpio0: gpio@c8004000 {
+                       compatible = "intel,ixp4xx-gpio";
+                       reg = <0xc8004000 0x1000>;
+diff -ruN a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile