arm64: Handle trapped DC CVADP

The ARMv8.5 DC CVADP instruction may be trapped to EL1 via
SCTLR_EL1.UCI therefore let's provide a handler for it.

Just like the CVAP instruction we use a 'sys' instruction instead of
the 'dc' alias to avoid build issues with older toolchains.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 3541720189c95c728360e7f78833438e330a8373..0e27fe91d5ea8e0e2703f89754da159ea6c90cd9 100644 (file)
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -196,9 +196,10 @@
 /*
  * User space cache operations have the following sysreg encoding
  * in System instructions.
- * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0)
+ * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
  */
 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
+#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP  12
 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU  11
 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC  10

diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 74598396e0bf4c71b00cb345fbef329d0ce9d694..21e73954762ca30c97063b9f36bfdbc387762d05 100644 (file)
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -459,6 +459,9 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
        case ESR_ELx_SYS64_ISS_CRM_DC_CVAC:     /* DC CVAC, gets promoted */
                __user_cache_maint("dc civac", address, ret);
                break;
+       case ESR_ELx_SYS64_ISS_CRM_DC_CVADP:    /* DC CVADP */
+               __user_cache_maint("sys 3, c7, c13, 1", address, ret);
+               break;
        case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:     /* DC CVAP */
                __user_cache_maint("sys 3, c7, c12, 1", address, ret);
                break;