drm/i915/gvt: Add mmio handler for for BXT.

Leverage most SKL/KBL mmio init info and add different mmio to
BXT specific function init_bxt_mmio_info().

Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 4dfe8ba5584900ab300bd67e47bd9064e44b8e80..0bc0c5418adb83c5868f051de0ba13bdb62db04f 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -257,7 +257,8 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
        new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
 
        if (IS_SKYLAKE(vgpu->gvt->dev_priv)
-               || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
+               || IS_KABYLAKE(vgpu->gvt->dev_priv)
+               || IS_BROXTON(vgpu->gvt->dev_priv)) {
                switch (offset) {
                case FORCEWAKE_RENDER_GEN9_REG:
                        ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
@@ -863,7 +864,8 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
        data = vgpu_vreg(vgpu, offset);
 
        if ((IS_SKYLAKE(vgpu->gvt->dev_priv)
-               || IS_KABYLAKE(vgpu->gvt->dev_priv))
+               || IS_KABYLAKE(vgpu->gvt->dev_priv)
+               || IS_BROXTON(vgpu->gvt->dev_priv))
                && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
                /* SKL DPB/C/D aux ctl register changed */
                return 0;
@@ -1370,6 +1372,16 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
                                *data0 = 0x1e1a1100;
                        else
                                *data0 = 0x61514b3d;
+               } else if (IS_BROXTON(vgpu->gvt->dev_priv)) {
+                       /**
+                        * "Read memory latency" command on gen9.
+                        * Below memory latency values are read
+                        * from Broxton MRB.
+                        */
+                       if (!*data0)
+                               *data0 = 0x16080707;
+                       else
+                               *data0 = 0x16161616;
                }
                break;
        case SKL_PCODE_CDCLK_CONTROL:
@@ -1427,8 +1439,11 @@ static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
 {
        u32 v = *(u32 *)p_data;
 
-       v &= (1 << 31) | (1 << 29) | (1 << 9) |
-            (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
+       if (IS_BROXTON(vgpu->gvt->dev_priv))
+               v &= (1 << 31) | (1 << 29);
+       else
+               v &= (1 << 31) | (1 << 29) | (1 << 9) |
+                       (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
        v |= (v >> 1);
 
        return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
@@ -1448,6 +1463,102 @@ static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
        return 0;
 }
 
+static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes)
+{
+       u32 v = *(u32 *)p_data;
+
+       if (v & BXT_DE_PLL_PLL_ENABLE)
+               v |= BXT_DE_PLL_LOCK;
+
+       vgpu_vreg(vgpu, offset) = v;
+
+       return 0;
+}
+
+static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes)
+{
+       u32 v = *(u32 *)p_data;
+
+       if (v & PORT_PLL_ENABLE)
+               v |= PORT_PLL_LOCK;
+
+       vgpu_vreg(vgpu, offset) = v;
+
+       return 0;
+}
+
+static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes)
+{
+       u32 v = *(u32 *)p_data;
+       u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
+
+       vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
+       vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
+       vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
+
+       vgpu_vreg(vgpu, offset) = v;
+
+       return 0;
+}
+
+static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes)
+{
+       u32 v = vgpu_vreg(vgpu, offset);
+
+       v &= ~UNIQUE_TRANGE_EN_METHOD;
+
+       vgpu_vreg(vgpu, offset) = v;
+
+       return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
+}
+
+static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes)
+{
+       u32 v = *(u32 *)p_data;
+
+       if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
+               vgpu_vreg(vgpu, offset - 0x600) = v;
+               vgpu_vreg(vgpu, offset - 0x800) = v;
+       } else {
+               vgpu_vreg(vgpu, offset - 0x400) = v;
+               vgpu_vreg(vgpu, offset - 0x600) = v;
+       }
+
+       vgpu_vreg(vgpu, offset) = v;
+
+       return 0;
+}
+
+static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
+               unsigned int offset, void *p_data, unsigned int bytes)
+{
+       u32 v = *(u32 *)p_data;
+
+       if (v & BIT(0)) {
+               vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
+                       ~PHY_RESERVED;
+               vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
+                       PHY_POWER_GOOD;
+       }
+
+       if (v & BIT(1)) {
+               vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
+                       ~PHY_RESERVED;
+               vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
+                       PHY_POWER_GOOD;
+       }
+
+
+       vgpu_vreg(vgpu, offset) = v;
+
+       return 0;
+}
+
 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
                unsigned int offset, void *p_data, unsigned int bytes)
 {
@@ -2671,17 +2782,17 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
        MMIO_D(_MMIO(0x45504), D_SKL_PLUS);
        MMIO_D(_MMIO(0x45520), D_SKL_PLUS);
        MMIO_D(_MMIO(0x46000), D_SKL_PLUS);
-       MMIO_DH(_MMIO(0x46010), D_SKL | D_KBL, NULL, skl_lcpll_write);
-       MMIO_DH(_MMIO(0x46014), D_SKL | D_KBL, NULL, skl_lcpll_write);
-       MMIO_D(_MMIO(0x6C040), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6C048), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6C050), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6C044), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6C04C), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6C054), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6c058), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6c05c), D_SKL | D_KBL);
-       MMIO_DH(_MMIO(0x6c060), D_SKL | D_KBL, dpll_status_read, NULL);
+       MMIO_DH(_MMIO(0x46010), D_SKL_PLUS, NULL, skl_lcpll_write);
+       MMIO_DH(_MMIO(0x46014), D_SKL_PLUS, NULL, skl_lcpll_write);
+       MMIO_D(_MMIO(0x6C040), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6C048), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6C050), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6C044), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6C04C), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6C054), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6c058), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6c05c), D_SKL_PLUS);
+       MMIO_DH(_MMIO(0x6c060), D_SKL_PLUS, dpll_status_read, NULL);
 
        MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
        MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
@@ -2806,53 +2917,57 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
        MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
        MMIO_D(_MMIO(0x7039c), D_SKL_PLUS);
 
-       MMIO_D(_MMIO(0x8f074), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x8f004), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x8f034), D_SKL | D_KBL);
+       MMIO_D(_MMIO(0x8f074), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x8f004), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x8f034), D_SKL_PLUS);
 
-       MMIO_D(_MMIO(0xb11c), D_SKL | D_KBL);
+       MMIO_D(_MMIO(0xb11c), D_SKL_PLUS);
 
-       MMIO_D(_MMIO(0x51000), D_SKL | D_KBL);
+       MMIO_D(_MMIO(0x51000), D_SKL_PLUS);
        MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS);
 
-       MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
-       MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
+       MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
+               NULL, NULL);
+       MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
+               NULL, NULL);
 
        MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
        MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
        MMIO_D(RC6_LOCATION, D_SKL_PLUS);
        MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
-       MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+       MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+               NULL, NULL);
 
        /* TRTT */
-       MMIO_DFH(_MMIO(0x4de0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_DFH(_MMIO(0x4de4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_DFH(_MMIO(0x4de8), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_DFH(_MMIO(0x4dec), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_DFH(_MMIO(0x4df0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
-       MMIO_DFH(_MMIO(0x4df4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write);
-       MMIO_DH(_MMIO(0x4dfc), D_SKL | D_KBL, NULL, gen9_trtt_chicken_write);
+       MMIO_DFH(_MMIO(0x4de0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+       MMIO_DFH(_MMIO(0x4de4), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+       MMIO_DFH(_MMIO(0x4de8), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+       MMIO_DFH(_MMIO(0x4dec), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+       MMIO_DFH(_MMIO(0x4df0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+       MMIO_DFH(_MMIO(0x4df4), D_SKL_PLUS, F_CMD_ACCESS,
+               NULL, gen9_trtte_write);
+       MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
 
-       MMIO_D(_MMIO(0x45008), D_SKL | D_KBL);
+       MMIO_D(_MMIO(0x45008), D_SKL_PLUS);
 
-       MMIO_D(_MMIO(0x46430), D_SKL | D_KBL);
+       MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
 
-       MMIO_D(_MMIO(0x46520), D_SKL | D_KBL);
+       MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
 
-       MMIO_D(_MMIO(0xc403c), D_SKL | D_KBL);
+       MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
        MMIO_D(_MMIO(0xb004), D_SKL_PLUS);
        MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
 
        MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
-       MMIO_D(_MMIO(0x1082c0), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x4068), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x67054), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6e560), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x6e554), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x2b20), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x65f00), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x65f08), D_SKL | D_KBL);
-       MMIO_D(_MMIO(0x320f0), D_SKL | D_KBL);
+       MMIO_D(_MMIO(0x1082c0), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
+       MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
 
        MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
        MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
@@ -2870,11 +2985,185 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 
        MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
        MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
-       MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
+       MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
                NULL, NULL);
 
        MMIO_D(_MMIO(0x4ab8), D_KBL);
-       MMIO_D(_MMIO(0x2248), D_SKL_PLUS | D_KBL);
+       MMIO_D(_MMIO(0x2248), D_KBL | D_SKL);
+
+       return 0;
+}
+
+static int init_bxt_mmio_info(struct intel_gvt *gvt)
+{
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
+       int ret;
+
+       MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
+
+       MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
+       MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
+       MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
+       MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
+       MMIO_D(ERROR_GEN6, D_BXT);
+       MMIO_D(DONE_REG, D_BXT);
+       MMIO_D(EIR, D_BXT);
+       MMIO_D(PGTBL_ER, D_BXT);
+       MMIO_D(_MMIO(0x4194), D_BXT);
+       MMIO_D(_MMIO(0x4294), D_BXT);
+       MMIO_D(_MMIO(0x4494), D_BXT);
+
+       MMIO_RING_D(RING_PSMI_CTL, D_BXT);
+       MMIO_RING_D(RING_DMA_FADD, D_BXT);
+       MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
+       MMIO_RING_D(RING_IPEHR, D_BXT);
+       MMIO_RING_D(RING_INSTPS, D_BXT);
+       MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
+       MMIO_RING_D(RING_BBSTATE, D_BXT);
+       MMIO_RING_D(RING_IPEIR, D_BXT);
+
+       MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
+
+       MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
+       MMIO_D(BXT_RP_STATE_CAP, D_BXT);
+       MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
+               NULL, bxt_phy_ctl_family_write);
+       MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
+               NULL, bxt_phy_ctl_family_write);
+       MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
+       MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
+       MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
+       MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
+               NULL, bxt_port_pll_enable_write);
+       MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
+               NULL, bxt_port_pll_enable_write);
+       MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
+               bxt_port_pll_enable_write);
+
+       MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
+       MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
+       MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
+       MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
+       MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
+       MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
+       MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
+       MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
+       MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
+
+       MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
+       MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
+       MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
+       MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
+       MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
+       MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
+       MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
+       MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
+       MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
+
+       MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
+               NULL, bxt_pcs_dw12_grp_write);
+       MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
+               bxt_port_tx_dw3_read, NULL);
+       MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
+
+       MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
+               NULL, bxt_pcs_dw12_grp_write);
+       MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
+               bxt_port_tx_dw3_read, NULL);
+       MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
+
+       MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
+               NULL, bxt_pcs_dw12_grp_write);
+       MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
+               bxt_port_tx_dw3_read, NULL);
+       MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
+       MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
+       MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
+
+       MMIO_D(BXT_DE_PLL_CTL, D_BXT);
+       MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
+       MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
+       MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
+
+       MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
+
+       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
+       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
+       MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
+
+       MMIO_D(RC6_CTX_BASE, D_BXT);
+
+       MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
+       MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
+       MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
+       MMIO_D(GEN6_GFXPAUSE, D_BXT);
+       MMIO_D(GEN8_L3SQCREG1, D_BXT);
+
+       MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
 
        return 0;
 }
@@ -2966,6 +3255,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
                ret = init_skl_mmio_info(gvt);
                if (ret)
                        goto err;
+       } else if (IS_BROXTON(dev_priv)) {
+               ret = init_broadwell_mmio_info(gvt);
+               if (ret)
+                       goto err;
+               ret = init_skl_mmio_info(gvt);
+               if (ret)
+                       goto err;
+               ret = init_bxt_mmio_info(gvt);
+               if (ret)
+                       goto err;
        }
 
        gvt->mmio.mmio_block = mmio_blocks;