pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Sat, 23 Feb 2019 22:39:55 +0000 (23:39 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 18 Mar 2019 15:56:50 +0000 (16:56 +0100)
The TDSELCTRL register is responsible for configuring the SDHI/MMC clock
return path delay and may be adjusted by the bootloader. Retain the value
across suspend/resume to prevent hardware instability after resume.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
drivers/pinctrl/sh-pfc/pfc-r8a77980.c
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
drivers/pinctrl/sh-pfc/pfc-r8a77995.c

index 287cfbb7e992f08807d3a6b624432c3c9c929da4..0ef7ada08316fa3434df67c04749ce615c2e716c 100644 (file)
@@ -5547,10 +5547,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
 
 enum ioctrl_regs {
        POCCTRL,
+       TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL] = { 0xe6060380, },
+       [TDSELCTRL] = { 0xe60603c0, },
        { /* sentinel */ },
 };
 
index db9add1405c54ff72f66c1c25b954f101caa7cd6..1a987dfea46f897a0ff8e8bf7b609a4dd0bf7f19 100644 (file)
@@ -5897,10 +5897,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
 
 enum ioctrl_regs {
        POCCTRL,
+       TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL] = { 0xe6060380, },
+       [TDSELCTRL] = { 0xe60603c0, },
        { /* sentinel */ },
 };
 
index 3481ff86938c6874d14068d62defb467e5ee7d68..a99c519e05a01f2392f3bf9708673f60ad21ca4f 100644 (file)
@@ -5855,10 +5855,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
 
 enum ioctrl_regs {
        POCCTRL,
+       TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL] = { 0xe6060380, },
+       [TDSELCTRL] = { 0xe60603c0, },
        { /* sentinel */ },
 };
 
index 14c4b671cddf46a1f929a709c9795f6af5d0a439..820b74ca9d10236b4f50211d1663a6677e70c3b9 100644 (file)
@@ -6012,10 +6012,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
 
 enum ioctrl_regs {
        POCCTRL,
+       TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL] = { 0xe6060380, },
+       [TDSELCTRL] = { 0xe60603c0, },
        { /* sentinel */ },
 };
 
index e2d1b49aaee6cc4ceae44c233e0e6923bb0a5b84..f5868f5e40189441fdd96506b270de5ec32b63b9 100644 (file)
@@ -2409,12 +2409,14 @@ enum ioctrl_regs {
        POCCTRL0,
        POCCTRL1,
        POCCTRL2,
+       TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL0] = { 0xe6060380 },
        [POCCTRL1] = { 0xe6060384 },
        [POCCTRL2] = { 0xe6060388 },
+       [TDSELCTRL] = { 0xe60603c0, },
        { /* sentinel */ },
 };
 
index 1dcc508366b89b4fe303f13aa69a646f88032ace..376e689c737821b5f92f18a98091f6bc9e9fb2ab 100644 (file)
@@ -2832,6 +2832,7 @@ enum ioctrl_regs {
        POCCTRL1,
        POCCTRL2,
        POCCTRL3,
+       TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
@@ -2839,6 +2840,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL1] = { 0xe6060384, },
        [POCCTRL2] = { 0xe6060388, },
        [POCCTRL3] = { 0xe606038c, },
+       [TDSELCTRL] = { 0xe60603c0, },
        { /* sentinel */ },
 };
 
index 7ed6c305a3d3e8f0682e19a6005d52409193b426..1a8d1ae896c0b0f5a43a9d9ffb3f598ba8a059a2 100644 (file)
@@ -4996,10 +4996,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 
 enum ioctrl_regs {
        POCCTRL0,
+       TDSELCTRL,
 };
 
 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL0] = { 0xe6060380, },
+       [TDSELCTRL] = { 0xe60603c0, },
        { /* sentinel */ },
 };
 
index 9e377e3b9cb3c20c8953f71e1784e9bd0d3fde87..0acdfb8bf0777b50a0a9aa3830e5f34c31865f03 100644 (file)
@@ -2833,6 +2833,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
        return bit;
 }
 
+enum ioctrl_regs {
+       TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+       [TDSELCTRL] = { 0xe60603c0, },
+       { /* sentinel */ },
+};
+
 static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
        .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
 };
@@ -2852,6 +2861,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
        .nr_functions = ARRAY_SIZE(pinmux_functions),
 
        .cfg_regs = pinmux_config_regs,
+       .ioctrl_regs = pinmux_ioctrl_regs,
 
        .pinmux_data = pinmux_data,
        .pinmux_data_size = ARRAY_SIZE(pinmux_data),