enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
enum ioctrl_regs {
POCCTRL,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
POCCTRL0,
POCCTRL1,
POCCTRL2,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL0] = { 0xe6060380 },
[POCCTRL1] = { 0xe6060384 },
[POCCTRL2] = { 0xe6060388 },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
POCCTRL1,
POCCTRL2,
POCCTRL3,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL1] = { 0xe6060384, },
[POCCTRL2] = { 0xe6060388, },
[POCCTRL3] = { 0xe606038c, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
enum ioctrl_regs {
POCCTRL0,
+ TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL0] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
return bit;
}
+enum ioctrl_regs {
+ TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [TDSELCTRL] = { 0xe60603c0, },
+ { /* sentinel */ },
+};
+
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
};
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),