drm/nouveau/fifo/gk104: fix engine status register offset

The offset should be 8 on Kepler and later.

Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index 8d5db6d5a5587ab13c3aa34f814f9af92b4bf01e..4fcd147d43c83d26132fb454d465bc4f282139b5 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -196,7 +196,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
 
        spin_lock_irqsave(&fifo->base.lock, flags);
        for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) {
-               u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
+               u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));
                u32 busy = (stat & 0x80000000);
                u32 next = (stat & 0x07ff0000) >> 16;
                u32 chsw = (stat & 0x00008000);