i915/dp/dsc: Add Rate Control Buffer Threshold Registers

Add register defines and  shifts that control the RC buffer threshold
between encoder and decoder for eDP/MIPI and DP cases.

The actual values are calculated usung a helper function.
This patch adds the shifts to registers where the value will
be written during atomic commit.

v2:
- Use _MMIO_PIPE() instead of _MMIO_(_PICK()) (Manasi)
- Combine shifts (Manasi)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-3-git-send-email-anusha.srivatsa@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e8687b0f906d6e41b21bfcd385d89f1815e6b2e4..5825319d4d22b3430760cbe7e3741f6792392889 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10499,4 +10499,55 @@ enum skl_power_gate {
 #define  DSC_SLICE_PER_LINE(slice_per_line)            ((slice_per_line) << 16)
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_aize)                (slice_chunk_size << 0)
 
+/* Icelake Rate Control Buffer Threshold Registers */
+#define DSCA_RC_BUF_THRESH_0                   _MMIO(0x6B230)
+#define DSCA_RC_BUF_THRESH_0_UDW               _MMIO(0x6B230 + 4)
+#define DSCC_RC_BUF_THRESH_0                   _MMIO(0x6BA30)
+#define DSCC_RC_BUF_THRESH_0_UDW               _MMIO(0x6BA30 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_0_PB           (0x78254)
+#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB       (0x78254 + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_0_PB           (0x78354)
+#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB       (0x78354 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_0_PC           (0x78454)
+#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC       (0x78454 + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_0_PC           (0x78554)
+#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC       (0x78554 + 4)
+#define ICL_DSC0_RC_BUF_THRESH_0(pipe)         _MMIO_PIPE((pipe) - PIPE_B, \
+                                               _ICL_DSC0_RC_BUF_THRESH_0_PB, \
+                                               _ICL_DSC0_RC_BUF_THRESH_0_PC)
+#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)     _MMIO_PIPE((pipe) - PIPE_B, \
+                                               _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
+                                               _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
+#define ICL_DSC1_RC_BUF_THRESH_0(pipe)         _MMIO_PIPE((pipe) - PIPE_B, \
+                                               _ICL_DSC1_RC_BUF_THRESH_0_PB, \
+                                               _ICL_DSC1_RC_BUF_THRESH_0_PC)
+#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)     _MMIO_PIPE((pipe) - PIPE_B, \
+                                               _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
+                                               _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
+
+#define DSCA_RC_BUF_THRESH_1                   _MMIO(0x6B238)
+#define DSCA_RC_BUF_THRESH_1_UDW               _MMIO(0x6B238 + 4)
+#define DSCC_RC_BUF_THRESH_1                   _MMIO(0x6BA38)
+#define DSCC_RC_BUF_THRESH_1_UDW               _MMIO(0x6BA38 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_1_PB           (0x7825C)
+#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB       (0x7825C + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_1_PB           (0x7835C)
+#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB       (0x7835C + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_1_PC           (0x7845C)
+#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC       (0x7845C + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_1_PC           (0x7855C)
+#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC       (0x7855C + 4)
+#define ICL_DSC0_RC_BUF_THRESH_1(pipe)         _MMIO_PIPE((pipe) - PIPE_B, \
+                                               _ICL_DSC0_RC_BUF_THRESH_1_PB, \
+                                               _ICL_DSC0_RC_BUF_THRESH_1_PC)
+#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)     _MMIO_PIPE((pipe) - PIPE_B, \
+                                               _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
+                                               _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
+#define ICL_DSC1_RC_BUF_THRESH_1(pipe)         _MMIO_PIPE((pipe) - PIPE_B, \
+                                               _ICL_DSC1_RC_BUF_THRESH_1_PB, \
+                                               _ICL_DSC1_RC_BUF_THRESH_1_PC)
+#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)     _MMIO_PIPE((pipe) - PIPE_B, \
+                                               _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
+                                               _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
+
 #endif /* _I915_REG_H_ */