powerpc/perf: Rearrange setting of ldbar for thread-imc

LDBAR holds the memory address allocated for each cpu. For thread-imc
the mode bit (i.e bit 1) of LDBAR is set to accumulation.
Currently, ldbar is loaded with per cpu memory address and mode set to
accumulation at boot time.

To enable trace-imc, the mode bit of ldbar should be set to 'trace'. So to
accommodate trace-mode of IMC, reposition setting of ldbar for thread-imc
to thread_imc_event_add(). Also reset ldbar at thread_imc_event_del().

Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c
index 2d12f0037e3a541b8e35814cad7d1820ebef9fac..23092a359ce07fe3c5e3d4aa5f5983bbc027b398 100644 (file)
--- a/arch/powerpc/perf/imc-pmu.c
+++ b/arch/powerpc/perf/imc-pmu.c
@@ -793,8 +793,11 @@ static int core_imc_event_init(struct perf_event *event)
 }
 
 /*
- * Allocates a page of memory for each of the online cpus, and write the
- * physical base address of that page to the LDBAR for that cpu.
+ * Allocates a page of memory for each of the online cpus, and load
+ * LDBAR with 0.
+ * The physical base address of the page allocated for a cpu will be
+ * written to the LDBAR for that cpu, when the thread-imc event
+ * is added.
  *
  * LDBAR Register Layout:
  *
@@ -812,7 +815,7 @@ static int core_imc_event_init(struct perf_event *event)
  */
 static int thread_imc_mem_alloc(int cpu_id, int size)
 {
-       u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, cpu_id);
+       u64 *local_mem = per_cpu(thread_imc_mem, cpu_id);
        int nid = cpu_to_node(cpu_id);
 
        if (!local_mem) {
@@ -829,9 +832,7 @@ static int thread_imc_mem_alloc(int cpu_id, int size)
                per_cpu(thread_imc_mem, cpu_id) = local_mem;
        }
 
-       ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
-
-       mtspr(SPRN_LDBAR, ldbar_value);
+       mtspr(SPRN_LDBAR, 0);
        return 0;
 }
 
@@ -982,6 +983,7 @@ static int thread_imc_event_add(struct perf_event *event, int flags)
 {
        int core_id;
        struct imc_pmu_ref *ref;
+       u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id());
 
        if (flags & PERF_EF_START)
                imc_event_start(event, flags);
@@ -990,6 +992,9 @@ static int thread_imc_event_add(struct perf_event *event, int flags)
                return -EINVAL;
 
        core_id = smp_processor_id() / threads_per_core;
+       ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
+       mtspr(SPRN_LDBAR, ldbar_value);
+
        /*
         * imc pmus are enabled only when it is used.
         * See if this is triggered for the first time.
@@ -1021,11 +1026,7 @@ static void thread_imc_event_del(struct perf_event *event, int flags)
        int core_id;
        struct imc_pmu_ref *ref;
 
-       /*
-        * Take a snapshot and calculate the delta and update
-        * the event counter values.
-        */
-       imc_event_update(event);
+       mtspr(SPRN_LDBAR, 0);
 
        core_id = smp_processor_id() / threads_per_core;
        ref = &core_imc_refc[core_id];
@@ -1044,6 +1045,11 @@ static void thread_imc_event_del(struct perf_event *event, int flags)
                ref->refc = 0;
        }
        mutex_unlock(&ref->lock);
+       /*
+        * Take a snapshot and calculate the delta and update
+        * the event counter values.
+        */
+       imc_event_update(event);
 }
 
 /* update_pmu_ops : Populate the appropriate operations for "pmu" */