drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_dynamic_mg_power_gating()

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 22346bbe9a4c543802d08c73b91ad59d0e314422..16d1a429ec9fdfaa0532252cd943d13d39b87d0a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1926,10 +1926,9 @@ static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad
        uint32_t data, default_data;
 
        default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
-       if (enable == true)
-               data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-       else
-               data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
+       data = REG_SET_FIELD(data, RLC_PG_CNTL,
+                            DYN_PER_CU_PG_ENABLE,
+                            enable ? 1 : 0);
        if(default_data != data)
                WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
 }