drm/radeon: add get_allowed_info_register for cayman/TN
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Oct 2014 13:51:29 +0000 (09:51 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 19 Mar 2015 16:26:40 +0000 (12:26 -0400)
Registers that can be fetched from the info ioctl.

Tested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/nid.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h

index dab00812abaabeeeee6295041e730143c99fecba..e8a496ff007ee680d30a2bd688f30d094b58461c 100644 (file)
@@ -828,6 +828,35 @@ out:
        return err;
 }
 
+/**
+ * cayman_get_allowed_info_register - fetch the register for the info ioctl
+ *
+ * @rdev: radeon_device pointer
+ * @reg: register offset in bytes
+ * @val: register value
+ *
+ * Returns 0 for success or -EINVAL for an invalid register
+ *
+ */
+int cayman_get_allowed_info_register(struct radeon_device *rdev,
+                                    u32 reg, u32 *val)
+{
+       switch (reg) {
+       case GRBM_STATUS:
+       case GRBM_STATUS_SE0:
+       case GRBM_STATUS_SE1:
+       case SRBM_STATUS:
+       case SRBM_STATUS2:
+       case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
+       case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
+       case UVD_STATUS:
+               *val = RREG32(reg);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 int tn_get_temp(struct radeon_device *rdev)
 {
        u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
index 6b44580440d09a10053abcb53bf6f6c048d4e063..2e5cdc4e98a1d0eda700c918532d422a73c3477d 100644 (file)
 #define UVD_UDEC_DBW_ADDR_CONFIG                       0xEF54
 #define UVD_RBC_RB_RPTR                                        0xF690
 #define UVD_RBC_RB_WPTR                                        0xF694
+#define UVD_STATUS                                     0xf6bc
 
 /*
  * PM4
index 0db4ee71fa698502ee24b9031ec261bcf61f3e8c..37d7cd7c6c463cabb9cf95925f027f56c52292e8 100644 (file)
@@ -1668,6 +1668,7 @@ static struct radeon_asic cayman_asic = {
        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
        .get_xclk = &rv770_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = cayman_get_allowed_info_register,
        .gart = {
                .tlb_flush = &cayman_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
@@ -1772,6 +1773,7 @@ static struct radeon_asic trinity_asic = {
        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
        .get_xclk = &r600_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = cayman_get_allowed_info_register,
        .gart = {
                .tlb_flush = &cayman_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
index b632e35248b1025bfe5f058bb10c0f8a21d81f81..dca6bc89bc1cdc05006568b1825fb4c1d0d0310e 100644 (file)
@@ -651,6 +651,8 @@ uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
                             struct radeon_ring *ring);
 void cayman_dma_set_wptr(struct radeon_device *rdev,
                         struct radeon_ring *ring);
+int cayman_get_allowed_info_register(struct radeon_device *rdev,
+                                    u32 reg, u32 *val);
 
 int ni_dpm_init(struct radeon_device *rdev);
 void ni_dpm_setup_asic(struct radeon_device *rdev);