drm/amd/display: fix dcn fe reset memory access error

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e1298d7029e6a23c329164f6fec23d6c2c1595e6..fa19c6b92f290dc1534c1ad96ae96df7d96e3529 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -853,8 +853,9 @@ static void plane_atomic_disable(struct core_dc *dc,
        struct dce_hwseq *hws = dc->hwseq;
        struct mem_input *mi = dc->res_pool->mis[fe_idx];
        struct mpc *mpc = dc->res_pool->mpc;
+       int opp_id = mi->opp_id;
 
-       if (mi->opp_id == 0xf)
+       if (opp_id == 0xf)
                return;
 
        mpc->funcs->wait_for_idle(mpc, mi->mpcc_id);
@@ -876,8 +877,8 @@ static void plane_atomic_disable(struct core_dc *dc,
        REG_UPDATE(DPP_CONTROL[fe_idx],
                        DPP_CLOCK_ENABLE, 0);
 
-       if (dc->res_pool->opps[mi->opp_id]->mpc_tree.num_pipes == 0)
-               REG_UPDATE(OPP_PIPE_CONTROL[mi->opp_id],
+       if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
+               REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
                                OPP_PIPE_CLOCK_EN, 0);
 
        if (dc->public.debug.sanity_checks)