Flush the writes to IRQSTATUS_L0 register in the DMA interrupt handler by reading the register
directly after write. This prevents the spurious DMA interrupts noted when using VDD_OPP 1
Signed-off-by: Mathias Nyman <mathias.nyman@nokia.com>
Acked-by: Santosh Shilimkar <Santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
dma_write(1 << ch, IRQSTATUS_L0);
+ /* read back the register to flush the write */
+ dma_read(IRQSTATUS_L0);
/* If the ch is not chained then chain_id will be -1 */
if (dma_chan[ch].chain_id != -1) {