drm/amdgpu: add amdgpu interface to query cu info
authorFlora Cui <flora.cui@amd.com>
Sat, 9 Dec 2017 04:08:40 +0000 (23:08 -0500)
committerOded Gabbay <oded.gabbay@gmail.com>
Sat, 9 Dec 2017 04:08:40 +0000 (23:08 -0500)
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

index bbe06e04dcb65f1936096b734a55e2423bf71f00..e40c5df55f95f8c6f2ba69ff4f15eeb5a1d1cc16 100644 (file)
@@ -959,6 +959,7 @@ struct amdgpu_gfx_config {
 };
 
 struct amdgpu_cu_info {
+       uint32_t simd_per_cu;
        uint32_t max_waves_per_simd;
        uint32_t wave_front_size;
        uint32_t max_scratch_slots_per_cu;
index 01aa851938f811b631ed4cca0c3ca3062ad5d3bf..48c1675aa342cec7f9a0c83eef446b519bfd8185 100644 (file)
@@ -304,3 +304,26 @@ uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 
        return amdgpu_dpm_get_sclk(adev, false) / 100;
 }
+
+void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+       struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
+
+       memset(cu_info, 0, sizeof(*cu_info));
+       if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
+               return;
+
+       cu_info->cu_active_number = acu_info.number;
+       cu_info->cu_ao_mask = acu_info.ao_cu_mask;
+       memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
+              sizeof(acu_info.bitmap));
+       cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
+       cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
+       cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
+       cu_info->simd_per_cu = acu_info.simd_per_cu;
+       cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
+       cu_info->wave_front_size = acu_info.wave_front_size;
+       cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
+       cu_info->lds_size = acu_info.lds_size;
+}
index 8d689ab7e4291fad585448c6e679aa32556facff..a8fa2253817b14cc39d7d14525d97387ebc703ae 100644 (file)
@@ -60,6 +60,7 @@ uint64_t get_vmem_size(struct kgd_dev *kgd);
 uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
 
 uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
+void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info);
 
 #define read_user_wptr(mmptr, wptr, dst)                               \
        ({                                                              \
index 12feba8091df0b72ac3b6d20f142e19b635c040a..c9b98d09a09b36f18ac0b3102e92fc10c337810e 100644 (file)
@@ -200,6 +200,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
        .get_fw_version = get_fw_version,
        .set_scratch_backing_va = set_scratch_backing_va,
        .get_tile_config = get_tile_config,
+       .get_cu_info = get_cu_info
 };
 
 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
index b38049569264f55c310833210ab56afff353d732..c538e3029f6fb24728733b8c3634692cf3f4cd8a 100644 (file)
@@ -161,6 +161,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
        .get_fw_version = get_fw_version,
        .set_scratch_backing_va = set_scratch_backing_va,
        .get_tile_config = get_tile_config,
+       .get_cu_info = get_cu_info
 };
 
 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
index 83d94c23aa782846367a90a828d7137d7a464aeb..9c62ebd5a19c2281c4b487cfc62cb544f511b49a 100644 (file)
@@ -48,6 +48,8 @@
 #include "oss/oss_2_0_d.h"
 #include "oss/oss_2_0_sh_mask.h"
 
+#define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
+
 #define GFX7_NUM_GFX_RINGS     1
 #define GFX7_MEC_HPD_SIZE      2048
 
@@ -5277,6 +5279,11 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
 
        cu_info->number = active_cu_number;
        cu_info->ao_cu_mask = ao_cu_mask;
+       cu_info->simd_per_cu = NUM_SIMD_PER_CU;
+       cu_info->max_waves_per_simd = 10;
+       cu_info->max_scratch_slots_per_cu = 32;
+       cu_info->wave_front_size = 64;
+       cu_info->lds_size = 64;
 }
 
 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
index 46550b5889825fef90c56a69f00ce01c49dc5df6..e18c2e62a20bb4f476012a2d8844f030bd917996 100644 (file)
@@ -7116,6 +7116,11 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
 
        cu_info->number = active_cu_number;
        cu_info->ao_cu_mask = ao_cu_mask;
+       cu_info->simd_per_cu = NUM_SIMD_PER_CU;
+       cu_info->max_waves_per_simd = 10;
+       cu_info->max_scratch_slots_per_cu = 32;
+       cu_info->wave_front_size = 64;
+       cu_info->lds_size = 64;
 }
 
 const struct amdgpu_ip_block_version gfx_v8_0_ip_block =