cxgb4/cxgb4vf: For T6 adapter, set FBMIN to 64 bytes

T4 and T5 hardware will not coalesce Free List PCI-E Fetch Requests if
the Host Driver provides more Free List Pointers than the Fetch Burst
Minimum value.  So if we set FBMIN to 64 bytes and the Host Driver
supplies 128 bytes of Free List Pointer data, the hardware will issue two
64-byte PCI-E Fetch Requests rather than a single coallesced 128-byte
Fetch Request. T6 fixes this. So, for T4/T5 we set the FBMIN value to 128

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index 22d972030927503e7e333d793f4aa88519ce2532..deca4a2956cc005fb8adce0b59a1c445699cce8d 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -2611,8 +2611,18 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
                                htonl(FW_IQ_CMD_FL0CNGCHMAP_V(cong) |
                                      FW_IQ_CMD_FL0CONGCIF_F |
                                      FW_IQ_CMD_FL0CONGEN_F);
+               /* In T6, for egress queue type FL there is internal overhead
+                * of 16B for header going into FLM module.  Hence the maximum
+                * allowed burst size is 448 bytes.  For T4/T5, the hardware
+                * doesn't coalesce fetch requests if more than 64 bytes of
+                * Free List pointers are provided, so we use a 128-byte Fetch
+                * Burst Minimum there (T6 implements coalescing so we can use
+                * the smaller 64-byte value there).
+                */
                c.fl0dcaen_to_fl0cidxfthresh =
-                       htons(FW_IQ_CMD_FL0FBMIN_V(FETCHBURSTMIN_64B_X) |
+                       htons(FW_IQ_CMD_FL0FBMIN_V(chip <= CHELSIO_T5 ?
+                                                  FETCHBURSTMIN_128B_X :
+                                                  FETCHBURSTMIN_64B_X) |
                              FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
                                                   FETCHBURSTMAX_512B_X :
                                                   FETCHBURSTMAX_256B_X));

diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
index a5231fa771db99a670c257d4c28adadeeea64b75..36cf3073ca37d59c2cf3a129603637fc54619c13 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
@@ -65,6 +65,7 @@
 #define TIMERREG_COUNTER0_X            0
 
 #define FETCHBURSTMIN_64B_X            2
+#define FETCHBURSTMIN_128B_X           3
 
 #define FETCHBURSTMAX_256B_X           2
 #define FETCHBURSTMAX_512B_X           3

diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/sge.c b/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
index 9772aad22bca2dcdd1aa711441b4a6482304ad7f..ba6a4e3471f063e64c3d55d51bf7e6c17ea41c48 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/sge.c
@@ -2300,9 +2300,20 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
                                FW_IQ_CMD_FL0HOSTFCMODE_V(SGE_HOSTFCMODE_NONE) |
                                FW_IQ_CMD_FL0PACKEN_F |
                                FW_IQ_CMD_FL0PADEN_F);
+
+               /* In T6, for egress queue type FL there is internal overhead
+                * of 16B for header going into FLM module.  Hence the maximum
+                * allowed burst size is 448 bytes.  For T4/T5, the hardware
+                * doesn't coalesce fetch requests if more than 64 bytes of
+                * Free List pointers are provided, so we use a 128-byte Fetch
+                * Burst Minimum there (T6 implements coalescing so we can use
+                * the smaller 64-byte value there).
+                */
                cmd.fl0dcaen_to_fl0cidxfthresh =
                        cpu_to_be16(
-                               FW_IQ_CMD_FL0FBMIN_V(SGE_FETCHBURSTMIN_64B) |
+                               FW_IQ_CMD_FL0FBMIN_V(chip <= CHELSIO_T5 ?
+                                                    FETCHBURSTMIN_128B_X :
+                                                    FETCHBURSTMIN_64B_X) |
                                FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
                                                     FETCHBURSTMAX_512B_X :
                                                     FETCHBURSTMAX_256B_X));