drm/i915/gvt: Fix shadow ctx ppgtt destroy function

Recently gvt shadow ctx create ppgtt table and this ppgtt's root
pointer is modified at workload dispatch, then we lose the original
ppgtt's root pointer, this causes the ppgtt destroy function abnormal
as it will release the wrong root table.

This patch save i915 context ppgtt root pointer at shadow
ctx creation and restore it at shadow ctx destruction.

v2: Split save and restore function (Zhenyu)

Fixes:4f15665ccbba("drm/i915: Add ppgtt to GVT GEM context")
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 31f6cdbe5c424f67f29167be34496e67fcb67b85..b4ab1dad01434f9ebdd6375104433a28c1707f2a 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -159,6 +159,10 @@ struct intel_vgpu_submission {
        struct kmem_cache *workloads;
        atomic_t running_workload_num;
        struct i915_gem_context *shadow_ctx;
+       union {
+               u64 i915_context_pml4;
+               u64 i915_context_pdps[GEN8_3LVL_PDPES];
+       };
        DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
        DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
        void *ring_scan_buffer[I915_NUM_ENGINES];

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index b8fbe3fabea3062203ad64d5ff33fd4ceebf0da2..1ad8c5e1455d782160d15c4a1c83cb6f64dad3cf 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1079,6 +1079,21 @@ err:
        return ret;
 }
 
+static void
+i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
+{
+       struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
+       int i;
+
+       if (i915_vm_is_48bit(&i915_ppgtt->vm))
+               px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
+       else {
+               for (i = 0; i < GEN8_3LVL_PDPES; i++)
+                       px_dma(i915_ppgtt->pdp.page_directory[i]) =
+                                               s->i915_context_pdps[i];
+       }
+}
+
 /**
  * intel_vgpu_clean_submission - free submission-related resource for vGPU
  * @vgpu: a vGPU
@@ -1091,6 +1106,7 @@ void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
        struct intel_vgpu_submission *s = &vgpu->submission;
 
        intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
+       i915_context_ppgtt_root_restore(s);
        i915_gem_context_put(s->shadow_ctx);
        kmem_cache_destroy(s->workloads);
 }
@@ -1116,6 +1132,21 @@ void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
        s->ops->reset(vgpu, engine_mask);
 }
 
+static void
+i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
+{
+       struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
+       int i;
+
+       if (i915_vm_is_48bit(&i915_ppgtt->vm))
+               s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
+       else {
+               for (i = 0; i < GEN8_3LVL_PDPES; i++)
+                       s->i915_context_pdps[i] =
+                               px_dma(i915_ppgtt->pdp.page_directory[i]);
+       }
+}
+
 /**
  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
  * @vgpu: a vGPU
@@ -1138,6 +1169,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
        if (IS_ERR(s->shadow_ctx))
                return PTR_ERR(s->shadow_ctx);
 
+       i915_context_ppgtt_root_save(s);
+
        bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
 
        s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",