drm/i915: don't update GEN6_PMIMR when it's not needed

I did some brief tests and the "new_val = pmimr" condition usually
happens a few times after exiting games.

Note: This is also prep work to track the GEN6_PMIMR register state in
dev_priv->pm_imr. This happens in the next patch.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Add note to explain why we want this, as per the discussion
between Chris and Paulo.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index af5c335a69db65f5b8af5a9b88b3617e50e37ef1..efe3fc671e1e56e24f127be58c24461a447a3714 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -142,14 +142,18 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
                              uint32_t interrupt_mask,
                              uint32_t enabled_irq_mask)
 {
-       uint32_t pmimr = I915_READ(GEN6_PMIMR);
-       pmimr &= ~interrupt_mask;
-       pmimr |= (~enabled_irq_mask & interrupt_mask);
+       uint32_t pmimr, new_val;
 
        assert_spin_locked(&dev_priv->irq_lock);
 
-       I915_WRITE(GEN6_PMIMR, pmimr);
-       POSTING_READ(GEN6_PMIMR);
+       pmimr = new_val = I915_READ(GEN6_PMIMR);
+       new_val &= ~interrupt_mask;
+       new_val |= (~enabled_irq_mask & interrupt_mask);
+
+       if (new_val != pmimr) {
+               I915_WRITE(GEN6_PMIMR, new_val);
+               POSTING_READ(GEN6_PMIMR);
+       }
 }
 
 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)