drm/i915: fix 64bit divide

ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined!

Store the frequency in kHz and drop 64bit divisions.

v2: Use div64_u64 (Matthew)

v3: store frequency in kHz to avoid 64bit divs (Chris/Ville)

Fixes: dab9178333 ("drm/i915: expose command stream timestamp frequency to userspace")
Reported-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113233455.12085-3-lionel.g.landwerlin@intel.com
Reviewed-by: Ewelina Musial <ewelina.musial@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 82ff186108f189c233d0c9dd42357d9e7577c0e4..6ba08b0c1c2269ffd2df4a68b003898bbdfef8a3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3269,8 +3269,8 @@ static int i915_engine_info(struct seq_file *m, void *unused)
                   yesno(dev_priv->gt.awake));
        seq_printf(m, "Global active requests: %d\n",
                   dev_priv->gt.active_requests);
-       seq_printf(m, "CS timestamp frequency: %llu Hz\n",
-                  dev_priv->info.cs_timestamp_frequency);
+       seq_printf(m, "CS timestamp frequency: %u kHz\n",
+                  dev_priv->info.cs_timestamp_frequency_khz);
 
        p = drm_seq_file_printer(m);
        for_each_engine(engine, dev_priv, id)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 42813f4247e29591430776f0f3a438a1e29399cd..171b86f37878cee5465b7472663d45d191f08b2b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -420,7 +420,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
                        return -ENODEV;
                break;
        case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
-               value = INTEL_INFO(dev_priv)->cs_timestamp_frequency;
+               value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
                break;
        default:
                DRM_DEBUG("Unknown parameter %d\n", param->param);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b538df740ac39e42f65bf162963058d528715fbf..2158a758a17d75750b3fc9df332aaa77ca60e145 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -885,7 +885,7 @@ struct intel_device_info {
        /* Slice/subslice/EU info */
        struct sseu_dev_info sseu;
 
-       u64 cs_timestamp_frequency;
+       u32 cs_timestamp_frequency_khz;
 
        struct color_luts {
                u16 degamma_lut_size;

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 78bf7374fbdde073f96c371125d21190207ed13e..f3e4940fed4993d171b1ef4a7bbb352bf27fe2d5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -329,29 +329,28 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
        sseu->has_eu_pg = 0;
 }
 
-static u64 read_reference_ts_freq(struct drm_i915_private *dev_priv)
+static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
 {
        u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
-       u64 base_freq, frac_freq;
+       u32 base_freq, frac_freq;
 
        base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
                     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
-       base_freq *= 1000000;
+       base_freq *= 1000;
 
        frac_freq = ((ts_override &
                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
                     GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
-       if (frac_freq != 0)
-               frac_freq = 1000000 / (frac_freq + 1);
+       frac_freq = 1000 / (frac_freq + 1);
 
        return base_freq + frac_freq;
 }
 
-static u64 read_timestamp_frequency(struct drm_i915_private *dev_priv)
+static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 {
-       u64 f12_5_mhz = 12500000;
-       u64 f19_2_mhz = 19200000;
-       u64 f24_mhz = 24000000;
+       u32 f12_5_mhz = 12500;
+       u32 f19_2_mhz = 19200;
+       u32 f24_mhz = 24000;
 
        if (INTEL_GEN(dev_priv) <= 4) {
                /* PRMs say:
@@ -360,7 +359,7 @@ static u64 read_timestamp_frequency(struct drm_i915_private *dev_priv)
                 *      hclks." (through the “Clocking Configuration”
                 *      (“CLKCFG”) MCHBAR register)
                 */
-               return (dev_priv->rawclk_freq * 1000) / 16;
+               return dev_priv->rawclk_freq / 16;
        } else if (INTEL_GEN(dev_priv) <= 8) {
                /* PRMs say:
                 *
@@ -371,7 +370,7 @@ static u64 read_timestamp_frequency(struct drm_i915_private *dev_priv)
                return f12_5_mhz;
        } else if (INTEL_GEN(dev_priv) <= 9) {
                u32 ctc_reg = I915_READ(CTC_MODE);
-               u64 freq = 0;
+               u32 freq = 0;
 
                if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
                        freq = read_reference_ts_freq(dev_priv);
@@ -389,7 +388,7 @@ static u64 read_timestamp_frequency(struct drm_i915_private *dev_priv)
                return freq;
        } else if (INTEL_GEN(dev_priv) <= 10) {
                u32 ctc_reg = I915_READ(CTC_MODE);
-               u64 freq = 0;
+               u32 freq = 0;
                u32 rpm_config_reg = 0;
 
                /* First figure out the reference frequency. There are 2 ways
@@ -553,7 +552,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                gen10_sseu_info_init(dev_priv);
 
        /* Initialize command stream timestamp frequency */
-       info->cs_timestamp_frequency = read_timestamp_frequency(dev_priv);
+       info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 
        DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
        DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
@@ -570,6 +569,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                         info->sseu.has_subslice_pg ? "y" : "n");
        DRM_DEBUG_DRIVER("has EU power gating: %s\n",
                         info->sseu.has_eu_pg ? "y" : "n");
-       DRM_DEBUG_DRIVER("CS timestamp frequency: %llu\n",
-                        info->cs_timestamp_frequency);
+       DRM_DEBUG_DRIVER("CS timestamp frequency: %u kHz\n",
+                        info->cs_timestamp_frequency_khz);
 }