pinctrl: qcom: Make the target processor value configurable

Currently the value used to specify that interrupts from the gpio should
be routed to the application processor is hardcoded for all Qualcomm SoCs.
But the new APQ8084 SoC uses a different value. To resolve this, we make
this value configurable for each SoC. For all existing SoCs we continue
to use the current value, and only for APQ8084 we use the new value.

Suggested-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c
index ef1263c7bdde735eaf7d11957cff5bf99c906a1c..c832d7d6b912989ff34dc56feb9fa132d5e88625 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -258,6 +258,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
                .intr_status_bit = 0,                   \
                .intr_ack_high = 1,                     \
                .intr_target_bit = 0,                   \
+               .intr_target_kpss_val = 4,              \
                .intr_raw_status_bit = 3,               \
                .intr_polarity_bit = 1,                 \
                .intr_detection_bit = 2,                \
@@ -283,6 +284,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
                .intr_enable_bit = -1,                  \
                .intr_status_bit = -1,                  \
                .intr_target_bit = -1,                  \
+               .intr_target_kpss_val = -1,             \
                .intr_raw_status_bit = -1,              \
                .intr_polarity_bit = -1,                \
                .intr_detection_bit = -1,               \

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c
index 5362959c448fbb607206a24cb2341fedec4975cb..138cbf6134a5816f98d46321bb31fd83225a5999 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -371,6 +371,7 @@ static const unsigned int sdc2_data_pins[] = { 152 };
                .intr_status_bit = 0,                   \
                .intr_ack_high = 0,                     \
                .intr_target_bit = 5,                   \
+               .intr_target_kpss_val = 3,              \
                .intr_raw_status_bit = 4,               \
                .intr_polarity_bit = 1,                 \
                .intr_detection_bit = 2,                \
@@ -396,6 +397,7 @@ static const unsigned int sdc2_data_pins[] = { 152 };
                .intr_enable_bit = -1,                  \
                .intr_status_bit = -1,                  \
                .intr_target_bit = -1,                  \
+               .intr_target_kpss_val = -1,             \
                .intr_raw_status_bit = -1,              \
                .intr_polarity_bit = -1,                \
                .intr_detection_bit = -1,               \

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
index 767cf1120b2073080a7d78749997bf4bf279ab90..81f49a9b4dbe794e21d2c5641e6ecf8a0d17de34 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -211,6 +211,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
                .intr_status_bit = 0,                   \
                .intr_ack_high = 1,                     \
                .intr_target_bit = 0,                   \
+               .intr_target_kpss_val = 4,              \
                .intr_raw_status_bit = 3,               \
                .intr_polarity_bit = 1,                 \
                .intr_detection_bit = 2,                \
@@ -236,6 +237,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
                .intr_enable_bit = -1,                  \
                .intr_status_bit = -1,                  \
                .intr_target_bit = -1,                  \
+               .intr_target_kpss_val = -1,             \
                .intr_raw_status_bit = -1,              \
                .intr_polarity_bit = -1,                \
                .intr_detection_bit = -1,               \

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 01eab47a746fd7b37766c22a0e7c081764c3ddc4..d5ed1272b928ecd4e3d4ecb3aca195fcedf23646 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -653,8 +653,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
        spin_unlock_irqrestore(&pctrl->lock, flags);
 }
 
-#define INTR_TARGET_PROC_APPS    4
-
 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -678,7 +676,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
        /* Route interrupts to application cpu */
        val = readl(pctrl->regs + g->intr_target_reg);
        val &= ~(7 << g->intr_target_bit);
-       val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
+       val |= g->intr_target_kpss_val << g->intr_target_bit;
        writel(val, pctrl->regs + g->intr_target_reg);
 
        /* Update configuration for gpio.

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 7b2a227a590aaf563763cd4beb5d3a06f6fc8a89..b952c4b4a8e9c3c0e4efb18c51491a9f1d14286f 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -53,6 +53,8 @@ struct msm_function {
  * @intr_status_bit:      Offset in @intr_status_reg for reading and acking the interrupt
  *                        status.
  * @intr_target_bit:      Offset in @intr_target_reg for configuring the interrupt routing.
+ * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
+ *                        this gpio should get routed to the KPSS processor.
  * @intr_raw_status_bit:  Offset in @intr_cfg_reg for the raw status bit.
  * @intr_polarity_bit:    Offset in @intr_cfg_reg for specifying polarity of the interrupt.
  * @intr_detection_bit:   Offset in @intr_cfg_reg for specifying interrupt type.
@@ -88,6 +90,7 @@ struct msm_pingroup {
        unsigned intr_ack_high:1;
 
        unsigned intr_target_bit:5;
+       unsigned intr_target_kpss_val:5;
        unsigned intr_raw_status_bit:5;
        unsigned intr_polarity_bit:5;
        unsigned intr_detection_bit:5;

diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c
index 35047036a053c1df2040ba590d0b9d6e395d053f..2ab21ce5575a4c9a538877a711aa099287114a68 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
@@ -384,6 +384,7 @@ static const unsigned int sdc3_data_pins[] = { 157 };
                .intr_status_bit = 0,                   \
                .intr_ack_high = 1,                     \
                .intr_target_bit = 0,                   \
+               .intr_target_kpss_val = 4,              \
                .intr_raw_status_bit = 3,               \
                .intr_polarity_bit = 1,                 \
                .intr_detection_bit = 2,                \
@@ -409,6 +410,7 @@ static const unsigned int sdc3_data_pins[] = { 157 };
                .intr_enable_bit = -1,                  \
                .intr_status_bit = -1,                  \
                .intr_target_bit = -1,                  \
+               .intr_target_kpss_val = -1,             \
                .intr_raw_status_bit = -1,              \
                .intr_polarity_bit = -1,                \
                .intr_detection_bit = -1,               \

diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
index 8c9720154d1e61fc2980b78eb96fa5333d6aa43b..3c858384d0418580596b258a80210112d74c4e4d 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
@@ -366,6 +366,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
                .intr_enable_bit = 0,                   \
                .intr_status_bit = 0,                   \
                .intr_target_bit = 5,                   \
+               .intr_target_kpss_val = 4,              \
                .intr_raw_status_bit = 4,               \
                .intr_polarity_bit = 1,                 \
                .intr_detection_bit = 2,                \
@@ -391,6 +392,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
                .intr_enable_bit = -1,                  \
                .intr_status_bit = -1,                  \
                .intr_target_bit = -1,                  \
+               .intr_target_kpss_val = -1,             \
                .intr_raw_status_bit = -1,              \
                .intr_polarity_bit = -1,                \
                .intr_detection_bit = -1,               \