drm/amdgpu: move PP_FEATURE_MASK to amd_shared header

It will be used not only for powerplay but also on amdgpu part in future
patches. So move it into amd_shared header file.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 354c6dc99481657f7bc14a4e0fae58a7c9125eb8..dd6203a0a6b77cd4d1f0e3bdb0b093fb1ccfdbd3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -52,8 +52,6 @@ enum amdgpu_dpm_event_src {
        AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
 };
 
-#define SCLK_DEEP_SLEEP_MASK 0x8
-
 struct amdgpu_ps {
        u32 caps; /* vbios flags */
        u32 class; /* vbios flags */

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index be6b19951e6a7d34bf664f9560c125b29465186f..f48168fbdfe6bb13a94e1388372e3c8fd4620915 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -5903,7 +5903,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
        pi->pcie_dpm_key_disabled = 0;
        pi->thermal_sclk_dpm_enabled = 0;
 
-       if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
+       if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
                pi->caps_sclk_ds = true;
        else
                pi->caps_sclk_ds = false;

diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index bc1720ea49591ff07c66cca69bfae9769da4de5b..ef668a321ef1e4a532e3faa8dd99f53a59f9bab7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2817,7 +2817,7 @@ static int kv_dpm_init(struct amdgpu_device *adev)
                pi->caps_tcp_ramping = true;
        }
 
-       if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
+       if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
                pi->caps_sclk_ds = true;
        else
                pi->caps_sclk_ds = false;

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 9fa3aaef3f331042bec0dadf84cbb28b55fd39ef..efeea9a9f27ef06bae51741b375220f1541ca97f 100644 (file)
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -109,6 +109,25 @@ enum amd_powergating_state {
 #define AMD_PG_SUPPORT_GFX_PIPELINE            (1 << 12)
 #define AMD_PG_SUPPORT_MMHUB                   (1 << 13)
 
+enum PP_FEATURE_MASK {
+       PP_SCLK_DPM_MASK = 0x1,
+       PP_MCLK_DPM_MASK = 0x2,
+       PP_PCIE_DPM_MASK = 0x4,
+       PP_SCLK_DEEP_SLEEP_MASK = 0x8,
+       PP_POWER_CONTAINMENT_MASK = 0x10,
+       PP_UVD_HANDSHAKE_MASK = 0x20,
+       PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
+       PP_VBI_TIME_SUPPORT_MASK = 0x80,
+       PP_ULV_MASK = 0x100,
+       PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
+       PP_CLOCK_STRETCH_MASK = 0x400,
+       PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
+       PP_SOCCLK_DPM_MASK = 0x1000,
+       PP_DCEFCLK_DPM_MASK = 0x2000,
+       PP_OVERDRIVE_MASK = 0x4000,
+       PP_ACG_MASK = 0x10000,
+};
+
 struct amd_ip_funcs {
        /* Name of IP block */
        char *name;

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 2f203ec3d19cf60bce73862414c47e2079758a8b..0d2b3cebd9cfd385a5e3f25a26f427bb300572f8 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -66,25 +66,6 @@ struct vi_dpm_table {
 #define PCIE_PERF_REQ_GEN2         3
 #define PCIE_PERF_REQ_GEN3         4
 
-enum PP_FEATURE_MASK {
-       PP_SCLK_DPM_MASK = 0x1,
-       PP_MCLK_DPM_MASK = 0x2,
-       PP_PCIE_DPM_MASK = 0x4,
-       PP_SCLK_DEEP_SLEEP_MASK = 0x8,
-       PP_POWER_CONTAINMENT_MASK = 0x10,
-       PP_UVD_HANDSHAKE_MASK = 0x20,
-       PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
-       PP_VBI_TIME_SUPPORT_MASK = 0x80,
-       PP_ULV_MASK = 0x100,
-       PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
-       PP_CLOCK_STRETCH_MASK = 0x400,
-       PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
-       PP_SOCCLK_DPM_MASK = 0x1000,
-       PP_DCEFCLK_DPM_MASK = 0x2000,
-       PP_OVERDRIVE_MASK = 0x4000,
-       PP_ACG_MASK = 0x10000,
-};
-
 enum PHM_BackEnd_Magic {
        PHM_Dummy_Magic       = 0xAA5555AA,
        PHM_RV770_Magic       = 0xDCBAABCD,