realtek/rtl839x: Edgecore ECS4100-12PH support
authorStijn Tintel <stijn@linux-ipv6.be>
Tue, 28 Jun 2022 14:44:51 +0000 (17:44 +0300)
committerStijn Tintel <stijn@linux-ipv6.be>
Fri, 9 Jan 2026 19:03:41 +0000 (21:03 +0200)
Add support for the Edgecore ECS4100-12PH, an 8-port 802.3bt PoE Gigabit
Ethernet switch with 2 combo RJ45/SFP and 2 SFP ports.

Hardware:
* SoC: RTL8393M
* RAM: 256MiB
* Flash: 32MiB SPI-NOR
* Ethernet:
  * 8x GbE RJ45 PoE (external RTL8218B)
  * 2x GbE RJ45 / SFP combo (external RTL8214FC)
  * 2x SFP (external RTL8214FC)
* Console: RJ45 RS232 port on front panel
* PoE: Nuvoton M0516 + 2x Broadcom BCM59121 PSE

Installation via bootloader:
* open serial console (baud rate 115200)
* interrupt boot process by pressing any key during boot
* boot the OpenWrt initramfs:
  # rtk network on
  # tftpboot 0x8f000000 /tftpboot/openwrt-realtek-rtl839x-edgecore_ecs4100-12ph-initramfs-kernel.bin
  # bootm
* copy openwrt-realtek-rtl839x-edgecore_ecs4100-12ph-squashfs-sysupgrade.bin
  to /tmp and use sysupgrade to install it:
  # sysupgrade /tmp/openwrt-realtek-rtl839x-edgecore_ecs4100-12ph-squashfs-sysupgrade.bin

Even though U-Boot claims the switch is based on the RTL8392M SoC, my
device is based on the RTL8393M SoC. I have confirmed this by removing
the heatsink, and the Linux kernel agrees with this. Therefore the DTS
has the rtl8393_ prefix.

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
target/linux/realtek/base-files/etc/board.d/02_network
target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts [new file with mode: 0644]
target/linux/realtek/image/rtl839x.mk

index 5a9757969a6bf429054f7330835341befeba672c..6e7227e1f23f00a1d28fa8f8bdfcba6f563a4367 100644 (file)
@@ -51,6 +51,14 @@ realtek_setup_macs()
        local label_mac=""
 
        case $board in
+       edgecore,ecs4100-12ph|\
+       tplink,sg2008p-v1|\
+       tplink,sg2210p-v3|\
+       tplink,sg2452p-v4|\
+       tplink,t1600g-28ts-v3)
+               label_mac=$(get_mac_label)
+               lan_mac="$label_mac"
+               ;;
        hpe,1920-8g|\
        hpe,1920-8g-poe-65w|\
        hpe,1920-8g-poe-180w|\
@@ -75,13 +83,6 @@ realtek_setup_macs()
                lan_mac_start=skip
                lan_mac="$(get_mac_label)"
        ;;
-       tplink,sg2008p-v1|\
-       tplink,sg2210p-v3|\
-       tplink,sg2452p-v4|\
-       tplink,t1600g-28ts-v3)
-               label_mac=$(get_mac_label)
-               lan_mac="$label_mac"
-               ;;
        tplink,tl-st1008f-v2|\
        zyxel,xgs1010-12-a1)
                lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)
@@ -132,6 +133,10 @@ realtek_setup_poe()
                ucidef_set_poe 193 "lan8 lan7 lan6 lan5 lan4 lan3 lan2 lan1 lan16 lan15 lan14 lan13 lan12 lan11 lan10 lan9 lan24 lan23
                                lan22 lan21 lan20 lan19 lan18 lan17"
                ;;
+       edgecore,ecs4100-12ph|\
+       netgear,gs110tpp-v1)
+               ucidef_set_poe 130 "$(filter_port_list "$lan_list" "lan9 lan10")"
+               ;;
        engenius,ews2910p-v1|\
        engenius,ews2910p-v3)
                ucidef_set_poe 60 "$(filter_port_list "$lan_list" "lan9 lan10")"
@@ -153,9 +158,6 @@ realtek_setup_poe()
                                lan22 lan21 lan20 lan19 lan18 lan17 lan32 lan31 lan30 lan29 lan28 lan27 lan26 lan25 lan40 lan39 lan38 lan37
                                lan36 lan35 lan34 lan33 lan48 lan47 lan46 lan45 lan44 lan43 lan42 lan41"
                ;;
-       netgear,gs110tpp-v1)
-               ucidef_set_poe 130 "$(filter_port_list "$lan_list" "lan9 lan10")"
-               ;;
        netgear,gs110tup-v1)
                ucidef_set_poe 240 "$(filter_port_list "$lan_list" "lan9 lan10")"
                ;;
diff --git a/target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts b/target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts
new file mode 100644 (file)
index 0000000..74d16ee
--- /dev/null
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl839x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       compatible = "edgecore,ecs4100-12ph", "realtek,rtl839x-soc";
+       model = "Edgecore ECS4100-12PH Switch";
+
+       aliases {
+               label-mac-device = &ethernet0;
+               led-boot = &led_sys;
+               led-failsafe = &led_sys;
+               led-running = &led_sys;
+               led-upgrade = &led_sys;
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x10000000>;
+       };
+
+       leds {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinmux_disable_sys_led>;
+               compatible = "gpio-leds";
+
+               led_sys: sys {
+                       label = "green:sys";
+                       gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+               };
+       };
+
+       gpio-restart {
+               compatible = "gpio-restart";
+               gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
+       };
+
+       i2c0: i2c-gpio-0 {
+               compatible = "i2c-gpio";
+               sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               i2c-gpio,delay-us = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       sfp0: sfp-p9 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c0>;
+               los-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+       };
+
+       i2c1: i2c-gpio-1 {
+               compatible = "i2c-gpio";
+               sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               i2c-gpio,delay-us = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       sfp1: sfp-p10 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c1>;
+               los-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+       };
+
+       i2c2: i2c-gpio-2 {
+               compatible = "i2c-gpio";
+               sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               i2c-gpio,delay-us = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       sfp2: sfp-p11 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c2>;
+               los-gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>;
+       };
+
+       i2c3: i2c-gpio-3 {
+               compatible = "i2c-gpio";
+               sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               i2c-gpio,delay-us = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       sfp3: sfp-p12 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c3>;
+               los-gpio = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+       };
+
+       i2c4: i2c-gpio-4 {
+               compatible = "i2c-gpio";
+               sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               i2c-gpio,delay-us = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               lm75b@48 {
+                       compatible = "nxp,lm75a";
+                       reg = <0x48>;
+               };
+
+               eeprom@56 {
+                       compatible = "atmel,24c32";
+                       reg = <0x56>;
+               };
+       };
+
+       watchdog {
+               compatible = "linux,wdt-gpio";
+               gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+               hw_algo = "toggle";
+               hw_margin_ms = <1200>;
+       };
+};
+
+&ethernet0 {
+       nvmem-cells = <&macaddr_factory>;
+       nvmem-cell-names = "mac-address";
+};
+
+&gpio0 {
+       poe_enable {
+               gpio-hog;
+               gpios = <16 GPIO_ACTIVE_HIGH>;
+               output-high;
+       };
+
+       poe_reset {
+               gpio-hog;
+               gpios = <18 GPIO_ACTIVE_HIGH>;
+               output-high;
+       };
+};
+
+&mdio_aux {
+       status = "okay";
+
+       gpio1: expander@3 {
+               compatible = "realtek,rtl8231";
+               reg = <3>;
+
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-ranges = <&gpio1 0 0 37>;
+
+               led-controller {
+                       compatible = "realtek,rtl8231-leds";
+                       status = "disabled";
+               };
+       };
+};
+
+&mdio_bus0 {
+       reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+       reset-delay-us = <2000>;
+       reset-post-delay-us = <140000>;
+
+       /* External phy RTL8218B */
+       EXTERNAL_PHY(0)
+       EXTERNAL_PHY(1)
+       EXTERNAL_PHY(2)
+       EXTERNAL_PHY(3)
+       EXTERNAL_PHY(4)
+       EXTERNAL_PHY(5)
+       EXTERNAL_PHY(6)
+       EXTERNAL_PHY(7)
+
+       /* External phy RTL8214FC */
+       EXTERNAL_SFP_PHY_FULL(48, 0)
+       EXTERNAL_SFP_PHY_FULL(49, 1)
+       EXTERNAL_SFP_PHY_FULL(50, 2)
+       EXTERNAL_SFP_PHY_FULL(51, 3)
+};
+
+&spi0 {
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "u-boot";
+                               reg = <0x0 0x40000>;
+                               read-only;
+                       };
+                       partition@100000 {
+                               compatible = "u-boot,env";
+                               label = "u-boot-env";
+                               reg = <0x100000 0x20000>;
+                       };
+                       partition@120000 {
+                               label = "empty";
+                               reg = <0x120000 0x60000>;
+                               read-only;
+                       };
+                       partition@180000 {
+                               label = "para";
+                               reg = <0x180000 0x20000>;
+                               read-only;
+
+                               nvmem-layout {
+                                       compatible = "fixed-layout";
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+
+                                       macaddr_factory: macaddr@0 {
+                                               reg = <0x0 0x6>;
+                                       };
+                               };
+                       };
+                       partition@200000 {
+                               label = "firmware";
+                               reg = <0x200000 0xdf0000>;
+                               compatible = "openwrt,uimage", "denx,uimage";
+                       };
+                       partition@ff0000 {
+                               label = "certificates";
+                               reg = <0xff0000 0x10000>;
+                       };
+               };
+       };
+};
+
+&switch0 {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               SWITCH_PORT_SDS(0, 1, 0, qsgmii)
+               SWITCH_PORT_SDS(1, 2, 0, qsgmii)
+               SWITCH_PORT_SDS(2, 3, 0, qsgmii)
+               SWITCH_PORT_SDS(3, 4, 0, qsgmii)
+               SWITCH_PORT_SDS(4, 5, 1, qsgmii)
+               SWITCH_PORT_SDS(5, 6, 1, qsgmii)
+               SWITCH_PORT_SDS(6, 7, 1, qsgmii)
+               SWITCH_PORT_SDS(7, 8, 1, qsgmii)
+
+               SWITCH_PORT_SDS(48, 9, 12, qsgmii)
+               SWITCH_PORT_SDS(49, 10, 12, qsgmii)
+               SWITCH_PORT_SDS(50, 11, 12, qsgmii)
+               SWITCH_PORT_SDS(51, 12, 12, qsgmii)
+
+               port@52 {
+                       ethernet = <&ethernet0>;
+                       reg = <52>;
+                       phy-mode = "internal";
+
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
+       };
+};
+
+&uart1 {
+       status = "okay";
+};
index 2412e5764e633263234e9db1badbe3ad42172786..755e9ce49cb5f036264e8d0e7a7e27a937514c61 100644 (file)
@@ -9,6 +9,21 @@ define Device/d-link_dgs-1210-52
 endef
 TARGET_DEVICES += d-link_dgs-1210-52
 
+define Device/edgecore_ecs4100-12ph
+  $(Device/uimage-rt-loader)
+  SOC := rtl8393
+  DEVICE_VENDOR := Edgecore
+  DEVICE_MODEL := ECS4100-12PH
+  IMAGE_SIZE := 14336k
+  DEVICE_PACKAGES := \
+       kmod-eeprom-at24 \
+       kmod-hwmon-adt7470 \
+       kmod-hwmon-lm75 \
+       kmod-thermal \
+       realtek-poe
+endef
+TARGET_DEVICES += edgecore_ecs4100-12ph
+
 define Device/hpe_1920-48g
   $(Device/hpe_1920)
   SOC := rtl8393