iwlwifi: dbg: fix debug monitor stop and restart delays
authorShahar S Matityahu <shahar.s.matityahu@intel.com>
Thu, 16 May 2019 07:31:17 +0000 (10:31 +0300)
committerLuca Coelho <luciano.coelho@intel.com>
Sat, 29 Jun 2019 07:09:41 +0000 (10:09 +0300)
The driver should delay only in recording stop flow between writing to
DBGC_IN_SAMPLE register and DBGC_OUT_CTRL register. Any other delay is
not needed.

Change the following:
1. Remove any unnecessary delays in the flow
2. Increase the delay in the stop recording flow since 100 micro is
   not enough
3. Use usleep_range instead of delay since the driver is allowed to
   sleep in this flow.

Signed-off-by: Shahar S Matityahu <shahar.s.matityahu@intel.com>
Fixes: 5cfe79c8d92a ("iwlwifi: fw: stop and start debugging using host command")
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
drivers/net/wireless/intel/iwlwifi/fw/dbg.c
drivers/net/wireless/intel/iwlwifi/fw/dbg.h

index b4c1599e032e7555441f74c499f04379112de04a..33a4bb56a39fae2c6ec451eaf1dda6ed2f47b1f5 100644 (file)
@@ -2386,8 +2386,6 @@ static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
        /* start recording again if the firmware is not crashed */
        if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) &&
            fwrt->fw->dbg.dest_tlv) {
-               /* wait before we collect the data till the DBGC stop */
-               udelay(500);
                iwl_fw_dbg_restart_recording(fwrt, &params);
        }
 
index 64f834a9134cf4641b6300c042892924a4cbd205..d7a285874973c0cc403bed4851aafb53d3dbf2e9 100644 (file)
@@ -295,7 +295,10 @@ _iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
        }
 
        iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
-       udelay(100);
+       /* wait for the DBGC to finish writing the internal buffer to DRAM to
+        * avoid halting the HW while writing
+        */
+       usleep_range(700, 1000);
        iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
 #ifdef CONFIG_IWLWIFI_DEBUGFS
        trans->dbg_rec_on = false;
@@ -325,7 +328,6 @@ _iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
                iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
        } else {
                iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
-               udelay(100);
                iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
        }
 }