drm/amd/pp: Implement update_dpm_settings on Tonga

use SW method to update DPM settings by updating SRAM
directly on Tonga.

Reviewed-by: Alex Deucher <alexdeucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index a268b98abb8e78898f3b47a1e51d772e3af899d8..86fb7709a1c4579335762d25a38a683d317e4039 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -3277,6 +3277,102 @@ static int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
                                array_size, SMC_RAM_END);
 }
 
+static int tonga_update_dpm_settings(struct pp_hwmgr *hwmgr,
+                               void *profile_setting)
+{
+       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+       struct tonga_smumgr *smu_data = (struct tonga_smumgr *)
+                       (hwmgr->smu_backend);
+       struct profile_mode_setting *setting;
+       struct SMU72_Discrete_GraphicsLevel *levels =
+                       smu_data->smc_state_table.GraphicsLevel;
+       uint32_t array = smu_data->smu7_data.dpm_table_start +
+                       offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
+
+       uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
+                       offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
+       struct SMU72_Discrete_MemoryLevel *mclk_levels =
+                       smu_data->smc_state_table.MemoryLevel;
+       uint32_t i;
+       uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
+
+       if (profile_setting == NULL)
+               return -EINVAL;
+
+       setting = (struct profile_mode_setting *)profile_setting;
+
+       if (setting->bupdate_sclk) {
+               if (!data->sclk_dpm_key_disabled)
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
+               for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
+                       if (levels[i].ActivityLevel !=
+                               cpu_to_be16(setting->sclk_activity)) {
+                               levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
+
+                               clk_activity_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
+                                               + offsetof(SMU72_Discrete_GraphicsLevel, ActivityLevel);
+                               offset = clk_activity_offset & ~0x3;
+                               tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
+                               tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
+                               cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+
+                       }
+                       if (levels[i].UpHyst != setting->sclk_up_hyst ||
+                               levels[i].DownHyst != setting->sclk_down_hyst) {
+                               levels[i].UpHyst = setting->sclk_up_hyst;
+                               levels[i].DownHyst = setting->sclk_down_hyst;
+                               up_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
+                                               + offsetof(SMU72_Discrete_GraphicsLevel, UpHyst);
+                               down_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
+                                               + offsetof(SMU72_Discrete_GraphicsLevel, DownHyst);
+                               offset = up_hyst_offset & ~0x3;
+                               tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
+                               tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
+                               tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
+                               cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+                       }
+               }
+               if (!data->sclk_dpm_key_disabled)
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
+       }
+
+       if (setting->bupdate_mclk) {
+               if (!data->mclk_dpm_key_disabled)
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
+               for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
+                       if (mclk_levels[i].ActivityLevel !=
+                               cpu_to_be16(setting->mclk_activity)) {
+                               mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
+
+                               clk_activity_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
+                                               + offsetof(SMU72_Discrete_MemoryLevel, ActivityLevel);
+                               offset = clk_activity_offset & ~0x3;
+                               tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
+                               tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
+                               cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+
+                       }
+                       if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
+                               mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
+                               mclk_levels[i].UpHyst = setting->mclk_up_hyst;
+                               mclk_levels[i].DownHyst = setting->mclk_down_hyst;
+                               up_hyst_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
+                                               + offsetof(SMU72_Discrete_MemoryLevel, UpHyst);
+                               down_hyst_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
+                                               + offsetof(SMU72_Discrete_MemoryLevel, DownHyst);
+                               offset = up_hyst_offset & ~0x3;
+                               tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
+                               tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
+                               tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
+                               cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+                       }
+               }
+               if (!data->mclk_dpm_key_disabled)
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
+       }
+       return 0;
+}
+
 const struct pp_smumgr_func tonga_smu_funcs = {
        .smu_init = &tonga_smu_init,
        .smu_fini = &smu7_smu_fini,
@@ -3300,4 +3396,5 @@ const struct pp_smumgr_func tonga_smu_funcs = {
        .initialize_mc_reg_table = tonga_initialize_mc_reg_table,
        .is_dpm_running = tonga_is_dpm_running,
        .populate_requested_graphic_levels = tonga_populate_requested_graphic_levels,
+       .update_dpm_settings = tonga_update_dpm_settings,
 };